公开(公告)号：US20240402426A1

公开(公告)日：2024-12-05

申请号：US18203321

申请日：2023-05-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Ryan Sporer ,  Karen Nummy

IPC: G02B6/124 ,  G02B6/13

Abstract: Structures for a photonics chip that include a reflector and methods of forming such structures. The structure comprises a reflector including a dielectric layer on a semiconductor substrate, a plurality of trenches in the dielectric layer, and a reflector layer. Each trench includes a plurality of sidewalls, and the reflector layer includes a portion on the sidewalls of each trench. The structure further comprises a photonic component over the reflector.

公开(公告)号：US12176351B2

公开(公告)日：2024-12-24

申请号：US17973618

申请日：2022-10-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ryan Sporer ,  George R. Mulfinger ,  Yusheng Bian

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L27/146 ,  H01L29/06

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

公开(公告)号：US20230047046A1

公开(公告)日：2023-02-16

申请号：US17973618

申请日：2022-10-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ryan Sporer ,  George R. Mulfinger ,  Yusheng Bian

IPC: H01L27/12 ,  H01L21/762 ,  H01L27/146 ,  H01L29/06 ,  H01L21/84

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

公开(公告)号：US20230038887A1

公开(公告)日：2023-02-09

申请号：US17394770

申请日：2021-08-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ryan Sporer ,  George R. Mulfinger ,  Yusheng Bian

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/06 ,  H01L21/762 ,  H01L27/146

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

公开(公告)号：US20210226044A1

公开(公告)日：2021-07-22

申请号：US16745833

申请日：2020-01-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander Derrickson ,  Edmund K. Banghart ,  Alexander Martin ,  Ryan Sporer ,  Jagar Singh ,  Katherina Babich ,  George R. Mulfinger

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first portion of a first semiconductor layer defines an emitter, a first portion of a second semiconductor layer defines a collector, and a base includes respective second portions of the first and second semiconductor layers that are laterally positioned between the first portion of the first semiconductor layer and the first portion of the second semiconductor layer. The first portion of the first semiconductor layer has a first thickness, and the first portion of the second semiconductor layer has a second thickness that is greater than the first thickness. The first portion and the second portion of the first semiconductor layer adjoin at a first junction having the first thickness. The first portion and the second portion of the second semiconductor layer adjoin at a second junction having the second thickness.

公开(公告)号：US11569268B1

公开(公告)日：2023-01-31

申请号：US17394770

申请日：2021-08-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ryan Sporer ,  George R. Mulfinger ,  Yusheng Bian

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/146 ,  H01L21/762 ,  H01L29/06

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

公开(公告)号：US11127843B2

公开(公告)日：2021-09-21

申请号：US16733528

申请日：2020-01-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson Holt ,  Alexander Derrickson ,  Ryan Sporer ,  George R. Mulfinger ,  Alexander Martin ,  Jagar Singh

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/10

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A base layer is positioned in a cavity in a semiconductor layer, a first terminal is coupled to the base layer, and a second terminal is coupled to a portion of the semiconductor layer. The second terminal is laterally spaced from the first terminal, and the portion of the semiconductor layer is laterally positioned between the second terminal and the base layer.

公开(公告)号：US11094805B2

公开(公告)日：2021-08-17

申请号：US16745833

申请日：2020-01-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander Derrickson ,  Edmund K. Banghart ,  Alexander Martin ,  Ryan Sporer ,  Jagar Singh ,  Katherina Babich ,  George R. Mulfinger

IPC: H01L29/737 ,  H01L29/08 ,  H01L21/324 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first portion of a first semiconductor layer defines an emitter, a first portion of a second semiconductor layer defines a collector, and a base includes respective second portions of the first and second semiconductor layers that are laterally positioned between the first portion of the first semiconductor layer and the first portion of the second semiconductor layer. The first portion of the first semiconductor layer has a first thickness, and the first portion of the second semiconductor layer has a second thickness that is greater than the first thickness. The first portion and the second portion of the first semiconductor layer adjoin at a first junction having the first thickness. The first portion and the second portion of the second semiconductor layer adjoin at a second junction having the second thickness.

公开(公告)号：US20210091212A1

公开(公告)日：2021-03-25

申请号：US16733528

申请日：2020-01-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson Holt ,  Alexander Derrickson ,  Ryan Sporer ,  George R. Mulfinger ,  Alexander Martin ,  Jagar Singh

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/10 ,  H01L21/3065 ,  H01L29/66

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A base layer is positioned in a cavity in a semiconductor layer, a first terminal is coupled to the base layer, and a second terminal is coupled to a portion of the semiconductor layer. The second terminal is laterally spaced from the first terminal, and the portion of the semiconductor layer is laterally positioned between the second terminal and the base layer.

公开(公告)号：US11650382B1

公开(公告)日：2023-05-16

申请号：US17510934

申请日：2021-10-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ryan Sporer ,  Yusheng Bian ,  Takako Hirokawa

IPC: H04B10/00 ,  G02B6/42 ,  G02B6/30

CPC classification number: G02B6/4251 ,  G02B6/305

Abstract: Structures including an optical component, such as an edge coupler, and methods of fabricating a structure that includes an optical component, such as an edge coupler. The structure includes a substrate having a sealed cavity, an optical component, and a dielectric layer between the optical component and the sealed cavity. The optical component is positioned vertically over the substrate and the dielectric layer, and the optical component overlaps with the sealed cavity in the substrate.