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    GENERATING INTEGRATED CIRCUIT FLOORPLANS USING NEURAL NETWORKS
    12.
    发明申请
    GENERATING INTEGRATED CIRCUIT FLOORPLANS USING NEURAL NETWORKS 审中-公开

    公开(公告)号：US20200175216A1

    公开(公告)日：2020-06-04

    申请号：US16703837

    申请日：2019-12-04

    Applicant: Google LLC

    Inventor： Chian-min Richard Ho ,  William Hang ,  Mustafa Nazim Yazgan ,  Anna Darling Goldie ,  Jeffrey Adgate Dean ,  Azalia Mirhoseini ,  Emre Tuncer ,  Ya Wang ,  Anand Babu

    IPC: G06F30/27 ,  G06F30/392

    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

    LEARNED GRAPH OPTIMIZATIONS FOR COMPILERS
    13.
    发明公开
    LEARNED GRAPH OPTIMIZATIONS FOR COMPILERS 审中-公开

    公开(公告)号：US20230176840A1

    公开(公告)日：2023-06-08

    申请号：US17921933

    申请日：2021-06-07

    Applicant: Google LLC

    Inventor： Yanqi Zhou ,  Sudip Roy ,  Amirali Abdolrashidi ,  Daniel Lin-Kit Wong ,  Chao Ma ,  Qiumin Xu ,  Hanxiao Liu ,  Phitchaya Mangpo Phothilimthana ,  Shen Wang ,  Anna Darling Goldie ,  Azalia Mirhoseini ,  James Laudon

    IPC: G06F8/41

    CPC classification number: G06F8/443

    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for compiler optimizations using a compiler optimization network. One of the methods includes receiving an input program, wherein the input program defines a graph of operation modules, wherein each node in the graph is a respective operation module, and each edge between nodes in the graph represents one operation module receiving the output generated by another operation module. The input program is processed by a compiler optimization network comprising a graph-embedding network that is configured to encode operation features and operation dependencies of the operation modules of the input program into a graph embedding representation and a policy network that is configured to generate an optimization action for each of one or more nodes encoded in the graph embedding representation. The compiler optimization network generates an output optimization plan comprising one or more optimization actions for the input program.

    HIERARCHICAL DEVICE PLACEMENT WITH REINFORCEMENT LEARNING
    16.
    发明申请
    HIERARCHICAL DEVICE PLACEMENT WITH REINFORCEMENT LEARNING 审中-公开

    公开(公告)号：US20190392294A1

    公开(公告)日：2019-12-26

    申请号：US16554217

    申请日：2019-08-28

    Applicant: Google LLC

    Inventor： Benoit Steiner ,  Anna Darling Goldie ,  Jeffrey Adgate Dean ,  Hieu Hy Pham ,  Azalia Mirhoseini ,  Quoc V. Le

    IPC: G06N3/04 ,  G06N20/00 ,  G06F16/901 ,  G06N3/063 ,  G06N3/08 ,  G06N5/04

    Abstract: A method for determining a placement for machine learning model operations across multiple hardware devices includes receiving data specifying machine learning operations, and determining a placement that assigns each of the operations specified by the data to a respective device from the multiple hardware devices. Determining the placement includes: generating, from the data, a respective operation embedding for each of the operations; grouping the operations into multiple operation groups, comprising processing each of the respective operation embeddings using a grouper neural network having multiple grouper parameters, in which the grouper neural network is configured to, for each of the operations, process the operation embedding for the operation in accordance with first values of the grouper parameters to generate a grouper output that assigns the operation to an operation group from the multiple operation groups; and assigning each of the operation groups to a respective device from the multiple hardware devices.

    GENERATING INTEGRATED CIRCUIT FLOORPLANS USING NEURAL NETWORKS
    19.
    发明申请
    GENERATING INTEGRATED CIRCUIT FLOORPLANS USING NEURAL NETWORKS 有权

    公开(公告)号：US20250053714A1

    公开(公告)日：2025-02-13

    申请号：US18805439

    申请日：2024-08-14

    Applicant: Google LLC

    Inventor： Chian-min Richard Ho ,  William Hang ,  Mustafa Nazim Yazgan ,  Anna Darling Goldie ,  Jeffrey Adgate Dean ,  Azalia Mirhoseini ,  Emre Tuncer ,  Ya Wang ,  Anand Babu

    IPC: G06F30/27 ,  G06F30/392

    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

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