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公开(公告)号:US10917310B2
公开(公告)日:2021-02-09
申请号:US16666658
申请日:2019-10-29
Applicant: Google LLC
Inventor: Chiu Wah Kelvin So , Jakub Ocwieja , Radu Jurca , Md Mahbubul Hasan , Daniel Svonava , Mahesh Keralapura Manjunatha , David Fan , Yao Liu , Xi Xiong , Andrei Dragus , Vinay Vyas Vemuri , Shen Wang , Muruo Liu
IPC: H04N21/466 , H04L12/24 , G06F16/953 , G06F30/20 , H04L12/26
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a content platform that receives a request to provide a digital component. The request includes information about users to which the digital component is directed. Futurized queries are obtained from serving logs of a serving system that is configured to execute an existing digital component using serving code that directs digital content to the set of users. The futurized queries are loaded as data structures in memory of a forecasting system. The system uses an instruction set derived from the serving code to determine that similarity between the particular futurized query and the request exceeds a threshold similarity. The system then generates a forecast output as a response to the request based on futurized queries that exceed the threshold similarity. The forecast output includes data describing future provision of the digital component.
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公开(公告)号:US11853677B2
公开(公告)日:2023-12-26
申请号:US18082392
申请日:2022-12-15
Applicant: Google LLC
Inventor: Anna Darling Goldie , Azalia Mirhoseini , Ebrahim Songhori , Wenjie Jiang , Shen Wang , Roger David Carpenter , Young-Joon Lee , Mustafa Nazim Yazgan , Chian-min Richard Ho , Quoc V. Le , James Laudon , Jeffrey Adgate Dean , Kavya Srinivasa Setty , Omkar Pathak
IPC: G06F30/392 , G06F30/398 , G06N3/08
CPC classification number: G06F30/392 , G06F30/398 , G06N3/08
Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.
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