公开(公告)号：US20240193093A1

公开(公告)日：2024-06-13

申请号：US18583341

申请日：2024-02-21

Applicant: Google LLC

Inventor： Jiazhen Zheng ,  Srinivas Vaduvatha ,  Hugh McEvoy Walsh ,  Prashant R. Chandra ,  Abhishek Agarwal ,  Weihuang Wang ,  Weiwei Jiang

IPC: G06F12/0895 ,  G06F12/0864 ,  G06F12/121

CPC classification number: G06F12/0895 ,  G06F12/0864 ,  G06F12/121

Abstract: A packet cache system includes a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; and an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high.

公开(公告)号：US11995000B2

公开(公告)日：2024-05-28

申请号：US17834018

申请日：2022-06-07

Applicant: Google LLC

Inventor： Jiazhen Zheng ,  Srinivas Vaduvatha ,  Hugh McEvoy Walsh ,  Prashant R. Chandra ,  Abhishek Agarwal ,  Weihuang Wang ,  Weiwei Jiang

IPC: G06F12/0895 ,  G06F12/0864 ,  G06F12/121

CPC classification number: G06F12/0895 ,  G06F12/0864 ,  G06F12/121

Abstract: A packet cache system includes a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; and an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high.

公开(公告)号：US20240168996A1

公开(公告)日：2024-05-23

申请号：US18423766

申请日：2024-01-26

Applicant: Google LLC

Inventor： Weiwei Jiang ,  Srinivas Vaduvatha ,  Prashant R. Chandra ,  Jiazhen Zheng ,  Hugh McEvoy Walsh ,  Weihuang Wang ,  Abhishek Agarwal

IPC: G06F16/901 ,  G06F3/06

CPC classification number: G06F16/9014 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G06F16/9017

Abstract: A hash table system, including a plurality of hash tables, associated with respective hash functions, for storing key-value pairs; an overflow memory for storing key-value pairs moved from the hash tables due to collision; and an arbiter for arbitrating among commands including update commands, match commands, and rehash commands, wherein for each system clock cycle, the arbiter selects as a selected command one of an update command, a match command, or a rehash command, and wherein the hash table system completes execution of each selected command within a bounded number of system clock cycles.

公开(公告)号：US20240121320A1

公开(公告)日：2024-04-11

申请号：US17961669

申请日：2022-10-07

Applicant: Google LLC

Inventor： Abhishek Agarwal ,  Weihuang Wang ,  Weiwei Jiang ,  Srinivas Vaduvatha ,  Jiazhen Zheng

IPC: H04L67/61 ,  H04L67/55

CPC classification number: H04L67/61 ,  H04L67/55

Abstract: Aspects of the disclosure are directed to a high performance connection scheduler for reliable transport protocols in data center networking. The connection scheduler can handle enqueue events, dequeue events, and update events. The connection scheduler can include a connection queue, scheduling queue, and quality of service arbiter to support scheduling a large number of connections at a high rate.

公开(公告)号：US20240111667A1

公开(公告)日：2024-04-04

申请号：US17954540

申请日：2022-09-28

Applicant: Google LLC

Inventor： Abhishek Agarwal ,  Srinivas Vaduvatha ,  Weiwei Jiang ,  Hugh McEvoy Walsh ,  Weihuang Wang ,  Jiazhen Zheng ,  Ajay Venkatesan

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F12/0292

Abstract: Aspects of the disclosure are directed to a memory allocator for assigning contiguous memory space for data packets in on-chip memory of a network interface card. The memory allocator includes a plurality of sub-allocators that correspond to a structure of entries, where each entry represents a quanta of memory allocation. The sub-allocators are organized in decreasing size in the memory allocator based on the amount of memory quanta they can allocate.