公开(公告)号：US07373486B2

公开(公告)日：2008-05-13

申请号：US11214193

申请日：2005-08-29

申请人： Wei-Han Lien ,  John K Yong ,  Shyam Sundar ,  Rajat Goel

发明人： Wei-Han Lien ,  John K Yong ,  Shyam Sundar ,  Rajat Goel

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3861

摘要： In one embodiment, a renamer comprises a plurality of storage locations and compare circuitry. Each storage location is assigned to a respective renameable resource and is configured to store an identifier corresponding to a youngest instruction operation that writes the respective renameable resource. Coupled to receive an input representing one or more retiring instruction identifiers corresponding to instruction operations that are being retired, the compare circuitry is configured to detect a match between at least a first identifier in a first storage location and one of the retiring identifiers. An encoded form of the identifiers is logically divided into a plurality of fields, and the input comprises a first plurality of bit vectors. Each of the first plurality of bit vectors corresponds to a respective field and includes a bit position for each possible value of the respective field.

摘要翻译： 在一个实施例中，重新映射器包括多个存储位置和比较电路。 每个存储位置被分配给相应的可重命名资源，并且被配置为存储对应于写入相应可重命名资源的最小指令操作的标识符。 耦合以接收表示与正在退休的指令操作相对应的一个或多个退休指令标识符的输入，所述比较电路被配置为检测第一存储位置中的至少第一标识符与退出标识符之一的匹配。 标识符的编码形式在逻辑上被划分为多个字段，并且输入包括第一多个比特向量。 第一多个位向量中的每一个对应于相应的场，并且包括相应场的每个可能值的比特位置。

公开(公告)号：US07187606B1

公开(公告)日：2007-03-06

申请号：US11208911

申请日：2005-08-22

申请人： Rajat Goel

发明人： Rajat Goel

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C2207/007

摘要： In one embodiment, a read port circuit includes a precharge circuit configured to precharge a first node in the read port circuit and a pulldown circuit coupled to the first node. The pulldown circuit is configured to conditionally discharge the first node responsive to a first plurality of wordline signals and a first plurality of data signals. Each of the wordline signals corresponds to a respective memory cell of a first plurality of memory cells, and each of the data signals corresponds to a respective memory cell and represents data stored in the respective memory cell. In some embodiments, the read port circuit may be included in a register file in an integrated circuit that also includes logic circuitry configured to generate an address for a read port.

摘要翻译： 在一个实施例中，读端口电路包括预充电电路，其被配置为对读端口电路中的第一节点进行预充电，以及耦合到第一节点的下拉电路。 下拉电路被配置为响应于第一多个字线信号和第一多个数据信号有条件地对第一节点放电。 每个字线信号对应于第一多个存储单元的相应存储单元，并且每个数据信号对应于相应的存储单元，并且表示存储在相应存储单元中的数据。 在一些实施例中，读端口电路可以被包括在集成电路中的寄存器文件中，该集成电路还包括被配置为生成读端口的地址的逻辑电路。

公开(公告)号：US20070041262A1

公开(公告)日：2007-02-22

申请号：US11208912

申请日：2005-08-22

申请人： Rajat Goel

发明人： Rajat Goel

IPC分类号： G11C8/00

CPC分类号： G11C11/412 ,  G11C7/10 ,  G11C8/16 ,  G11C2207/108

摘要： In one embodiment, a memory circuit comprises one or more first memory cells, each of the one or more first memory cells configured to store at least one bit; one or more second memory cells, each of the one or more second memory cells configured to store at least one bit; and one or more read port circuits physically located between the first memory cells and the second memory cells. Each of the read port circuits is coupled to receive the at least one bit from each of the first memory cells and each of the second memory cells, and each of the read port circuits is configured to output the at least one bit from a selected memory cell of the first memory cells and the second memory cells responsive to a plurality of wordline signals coupled to the read port circuit.

公开(公告)号：US20070041250A1

公开(公告)日：2007-02-22

申请号：US11208911

申请日：2005-08-22

申请人： Rajat Goel

发明人： Rajat Goel

IPC分类号： G11C7/10

CPC分类号： G11C7/12 ,  G11C2207/007

摘要： In one embodiment, a read port circuit comprises a precharge circuit configured to precharge a first node in the read port circuit and a pulldown circuit coupled to the first node. The pulldown circuit is configured to conditionally discharge the first node responsive to a first plurality of wordline signals and a first plurality of data signals. Each of the wordline signals corresponds to a respective memory cell of a first plurality of memory cells, and each of the data signals corresponds to a respective memory cell and represents data stored in the respective memory cell. In some embodiments, the read port circuit may be included in a register file in an integrated circuit that also comprises logic circuitry configured to generate an address for a read port.

摘要翻译： 在一个实施例中，读端口电路包括预充电电路，其被配置为对读端口电路中的第一节点进行预充电，以及耦合到第一节点的下拉电路。 下拉电路被配置为响应于第一多个字线信号和第一多个数据信号有条件地对第一节点放电。 每个字线信号对应于第一多个存储单元的相应存储单元，并且每个数据信号对应于相应的存储单元，并且表示存储在相应存储单元中的数据。 在一些实施例中，读端口电路可以包括在集成电路中的寄存器文件中，该集成电路还包括被配置为生成读端口的地址的逻辑电路。

公开(公告)号：US20060184783A1

公开(公告)日：2006-08-17

申请号：US11062301

申请日：2005-02-17

申请人： David Albert ,  Frank Krueger ,  Rajat Goel ,  Peter Gurevich ,  Anthony Hodsdon ,  Radu Magarint ,  Thomas Olsen ,  Rahul Patil ,  Cyra Richardson ,  Robert Sinclair ,  Richard Turner ,  Eric Vandenberg ,  Robert Wlodarczyk

发明人： David Albert ,  Frank Krueger ,  Rajat Goel ,  Peter Gurevich ,  Anthony Hodsdon ,  Radu Magarint ,  Thomas Olsen ,  Rahul Patil ,  Cyra Richardson ,  Robert Sinclair ,  Richard Turner ,  Eric Vandenberg ,  Robert Wlodarczyk

IPC分类号： G06F1/24 ,  G06F15/177

CPC分类号： H04N19/162 ,  H04N19/12 ,  H04N19/157 ,  H04N19/172

摘要： An improved system and method for an extensible codec architecture for digital images is provided. Executable software code may be operably coupled to a codec manager for requesting imaging operations to be performed on a digital image. The codec manager may receive the request to perform an imaging operation on the digital image and may select an imaging component, such as a codec, from one or more imaging components registered in the computer system for performing an imaging operation on the digital image. An arbitration manager may include functionality for requesting enumeration of the operations an imaging component may perform on a particular digital image. One or more pixel format converters may then convert the pixel format in the digital image to a pixel format supported by an imaging component installed on the system.

公开(公告)号：US20060184576A1

公开(公告)日：2006-08-17

申请号：US11062267

申请日：2005-02-17

申请人： David Albert ,  Frank Krueger ,  Rajat Goel ,  Peter Gurevich ,  Anthony Hodsdon ,  Radu Magarint ,  Thomas Olsen ,  Rahul Patil ,  Cyra Richardson ,  Robert Sinclair ,  Richard Turner ,  Eric Vandenberg ,  Robert Wlodarczyk

发明人： David Albert ,  Frank Krueger ,  Rajat Goel ,  Peter Gurevich ,  Anthony Hodsdon ,  Radu Magarint ,  Thomas Olsen ,  Rahul Patil ,  Cyra Richardson ,  Robert Sinclair ,  Richard Turner ,  Eric Vandenberg ,  Robert Wlodarczyk

IPC分类号： G06F17/00

CPC分类号： G06F16/58 ,  G06F16/48

摘要： An improved system and method for an extensible metadata architecture for digital images is provided. Executable software code may be operably coupled to a metadata query reader and a metadata query writer for requesting operations for manipulating metadata in an image file. The metadata query reader may be operably coupled to a decoder having a block reader for identifying metadata blocks in an image file and associating a metadata reader with each metadata block. Each metadata reader may then enumerate the metadata in the metadata block associated with that metadata reader. The metadata query writer may be operably coupled to an encoder having a block writer for associating a metadata writer with each metadata block to be written to an image file. Each metadata writer may then write metadata in the metadata block associated with that metadata writer.

摘要翻译： 提供了一种用于数字图像的可扩展元数据结构的改进的系统和方法。 可执行软件代码可以可操作地耦合到元数据查询阅读器和元数据查询写入器，用于请求操作以操纵图像文件中的元数据。 元数据查询读取器可以可操作地耦合到具有用于识别图像文件中的元数据块并将元数据读取器与每个元数据块相关联的块读取器的解码器。 然后，每个元数据读取器可以枚举与该元数据读取器相关联的元数据块中的元数据。 元数据查询写入器可以可操作地耦合到具有块写入器的编码器，用于将元数据写入器与要写入图像文件的每个元数据块相关联。 然后，每个元数据写入器可以在与该元数据写入器相关联的元数据块中写入元数据。

公开(公告)号：US09652242B2

公开(公告)日：2017-05-16

申请号：US13461950

申请日：2012-05-02

申请人： Rajat Goel ,  Sandeep Gupta ,  Yamini Modukuru

发明人： Rajat Goel ,  Sandeep Gupta ,  Yamini Modukuru

IPC分类号： G06F9/38

CPC分类号： G06F9/38

摘要： An apparatus and method for calculating flag bits is disclosed. The flag bits may be used in a processor utilizing branch predication. More particularly, the apparatus and method may be used to calculate a predicate that can be used by a branch unit to evaluate whether a branch is to be taken. In one embodiment, the apparatus is coupled to receive a condition code associated with an instruction, and flag bits generated responsive to execution of the instruction. The condition code is indicative of a condition to be checked resulting from execution of the instruction. The apparatus may then provide an indication of whether the condition is true.

公开(公告)号：US20140195558A1

公开(公告)日：2014-07-10

申请号：US13735820

申请日：2013-01-07

申请人： Raghotham Murthy ,  Rajat Goel

发明人： Raghotham Murthy ,  Rajat Goel

IPC分类号： G06F17/30

CPC分类号： G06F17/30545 ,  G06F17/30368 ,  G06F17/30457 ,  G06F17/3048 ,  G06F17/30864 ,  G06F17/30867

摘要： Techniques for a system capable of performing low-latency database query processing are disclosed herein. The system includes a gateway server and a plurality of worker nodes. The gateway server is configured to divide a database query, for a database containing data stored in a distributed storage cluster having a plurality of data nodes, into a plurality of partial queries and construct a query result based on a plurality of intermediate results. Each worker node of the plurality of worker nodes is configured to process a respective partial query of the plurality of partial queries by scanning data related to the respective partial query that stored on at least one data node of the distributed storage cluster and generate an intermediate result of the plurality of intermediate results that is stored in a memory of that worker node.

摘要翻译： 本文公开了能够执行低等待时间数据库查询处理的系统的技术。 该系统包括网关服务器和多个工作节点。 网关服务器被配置为将包含存储在具有多个数据节点的分布式存储集群中的数据的数据库的数据库查询划分为多个部分查询，并且基于多个中间结果构建查询结果。 多个工作节点的每个工作节点被配置为通过扫描与存储在分布式存储集群的至少一个数据节点上的相应部分查询相关的数据来处理多个部分查询的相应部分查询，并生成中间结果 存储在该工作节点的存储器中的多个中间结果。

公开(公告)号：US20130297918A1

公开(公告)日：2013-11-07

申请号：US13461950

申请日：2012-05-02

申请人： Rajat Goel ,  Sandeep Gupta ,  Yamini Modukuru

发明人： Rajat Goel ,  Sandeep Gupta ,  Yamini Modukuru

IPC分类号： G06F9/38

CPC分类号： G06F9/38

摘要： An apparatus and method for calculating flag bits is disclosed. The flag bits may be used in a processor utilizing branch predication. More particularly, the apparatus and method may be used to calculate a predicate that can be used by a branch unit to evaluate whether a branch is to be taken. In one embodiment, the apparatus is coupled to receive a condition code associated with an instruction, and flag bits generated responsive to execution of the instruction. The condition code is indicative of a condition to be checked resulting from execution of the instruction. The apparatus may then provide an indication of whether the condition is true.

摘要翻译： 公开了一种用于计算标志位的装置和方法。 标志位可以在使用分支预测的处理器中使用。 更具体地，该装置和方法可以用于计算可由分支单元使用以判断是否采用分支的谓词。 在一个实施例中，该装置被耦合以接收与指令相关联的条件码，以及响应于该指令的执行产生的标志位。 条件代码指示由执行指令导致的检查条件。 该装置然后可以提供条件是否为真的指示。

公开(公告)号：US20070139075A1

公开(公告)日：2007-06-21

申请号：US11304165

申请日：2005-12-15

申请人： Rajat Goel ,  Edgardo Klass ,  Andrew Demas ,  Shih-Chieh Wen ,  Honkai Tam

发明人： Rajat Goel ,  Edgardo Klass ,  Andrew Demas ,  Shih-Chieh Wen ,  Honkai Tam

IPC分类号： H03K19/173

CPC分类号： H03K19/173 ,  G01R31/31922 ,  H03K3/35606 ,  H03K3/356156

摘要： In one embodiment, a combined mux/storage circuit comprises a latch element, a plurality of passgates connected to the latch element, and logic circuitry. Each passgate has an input coupled to receive a signal representing a respective mux input and is configured to open and close responsive to respective pairs of control signals. The logic circuitry is coupled to receive a clock signal, a delayed clock signal, and mux select control signals, and is configured to generate pulses on the pair of control signals to control a passgate that has an input coupled to receive the signal representing a selected mux inputs, as indicated by the mux select control signals. The width of the pulses is dependent on the clock signal and the delayed clock signal. The latch element is configured to latch the signal representing the selected mux input in parallel with the selected mux input being driven as an output of the mux/storage circuit.

摘要翻译： 在一个实施例中，组合复用/存储电路包括锁存元件，连接到锁存元件的多个通孔和逻辑电路。 每个通道具有耦合以接收表示相应多路复用器输入的信号的输入，并且被配置为响应于相应的控制信号对而打开和关闭。 逻辑电路被耦合以接收时钟信号，延迟的时钟信号和多路复用选择控制信号，并且被配置为在所述一对控制信号上产生脉冲以控制传输门，其具有耦合的输入，以接收表示所选择的信号 多路复用器输入，如多路复用器选择控制信号所示。 脉冲宽度取决于时钟信号和延迟的时钟信号。 闩锁元件被配置为将所选择的多路复用器输入的信号与所选择的多路复用器输入并行地锁存，作为多路复用器/存储电路的输出被驱动。