公开(公告)号：US10026476B2

公开(公告)日：2018-07-17

申请号：US15521590

申请日：2014-11-25

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Leong Yap Chia ,  Ning Ge ,  Wai Mun Wong

IPC: G11C13/00 ,  B41J2/045

Abstract: A circuit comprising an input, a ground, a first switch, a second switch and a bi-polar memristor, wherein the first switch is a first transistor and a gate of the first transistor is connected to a line to instruct setting of the bi-polar memristor, and the second switch is a second transistor and a gate of the second transistor is connected to a line to instruct re-setting of the bi-polar memristor.

公开(公告)号：US20180147839A1

公开(公告)日：2018-05-31

申请号：US15877971

申请日：2018-01-23

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Ning Ge ,  Leong Yap Chia ,  Wai Mun Wong

IPC: B41J2/045 ,  G11C16/32 ,  G11C16/08

CPC classification number: B41J2/04541 ,  B41J2/04543 ,  B41J2/0458 ,  B41J2/04581 ,  B41J2/04586 ,  G11C16/08 ,  G11C16/32

Abstract: Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a plurality of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the plurality of cells. A column shift register is coupled to the column select ports of the plurality of cells, the column shift register having a register location for each column of the plurality of cells and having an input to receive a first input signal. A row shift register is coupled to row select ports of the plurality of cells, the row shift register having a register location for each row of the plurality of cells and having an input to receive a second input signal.

公开(公告)号：US09919517B2

公开(公告)日：2018-03-20

申请号：US15111247

申请日：2014-01-17

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Ning Ge ,  Leong Yap Chia ,  Wai Mun Wong

IPC: G11C16/08 ,  B41J2/045 ,  G11C16/32

CPC classification number: B41J2/04541 ,  B41J2/04543 ,  B41J2/0458 ,  B41J2/04581 ,  B41J2/04586 ,  G11C16/08 ,  G11C16/32

Abstract: Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a plurality of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the plurality of cells. A column shift register is coupled to the column select ports of the plurality of cells, the column shift register having a register location for each column of the plurality of cells and having an input to receive a first input signal. A row shift register is coupled to row select ports of the plurality of cells, the row shift register having a register location for each row of the plurality of cells and having an input to receive a second input signal.