公开(公告)号：US20180012900A1

公开(公告)日：2018-01-11

申请号：US15541986

申请日：2015-01-29

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Wai Mun Wong ,  Leong Yap Chia ,  Ning Ge

IPC: G11C16/04

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L27/1156

Abstract: The present subject matter relates to an integrated circuit comprising an erasable programmable read only memory (EPROM) array having a plurality of EPROM cells disposed in rows and columns, wherein one or more EPROM cells located at predetermined positions in the EPROM array are selectively dischargeable. The one or more EPROM cells comprise a EPROM transistor having a first conductive layer to store electrons upon the EPROM transistor being programmed and a control metal oxide semiconductor field-effect transistor (MOSFET) electrically connected to the first conductive layer to provide an electron leakage path to dissipate the electrons stored in the first conductive layer in a predetermined leak time period.

公开(公告)号：US20170243645A1

公开(公告)日：2017-08-24

申请号：US15521590

申请日：2014-11-25

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Leong Yap Chia ,  Ning Ge ,  Wai Mun Wong

IPC: G11C13/00 ,  B41J2/045

CPC classification number: G11C13/0038 ,  B41J2/04541 ,  B41J2/04586 ,  B41J2/17546 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/15 ,  G11C2213/74 ,  G11C2213/79

Abstract: A circuit comprising an input, a ground, a first switch, a second switch and a bi-polar memristor, wherein the first switch is a first transistor and a gate of the first transistor is connected to a line to instruct setting of the bi-polar memristor, and the second switch is a second transistor and a gate of the second transistor is connected to a line to instruct re-setting of the bi-polar memristor.

公开(公告)号：US10173420B2

公开(公告)日：2019-01-08

申请号：US15558618

申请日：2015-07-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Wai Mun Wong ,  Leong Yap Chia ,  Ning Ge

IPC: B41J2/05 ,  B41J2/16 ,  B41J2/14

Abstract: The present subject matter relates to a printhead assembly comprising a plurality of print nozzles in a nozzle array. Each of the plurality of print nozzles is coupled to a printhead firing resistor, the printhead firing resistor being individually addressable. A print control circuit is to actuate the printhead firing resistor. In accordance with one example implementation of the present subject matter, the print control circuit comprises pull-down resistors made of Tantalum-Aluminum (Ta—Al).

公开(公告)号：US10081178B2

公开(公告)日：2018-09-25

申请号：US15877971

申请日：2018-01-23

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Ning Ge ,  Leong Yap Chia ,  Wai Mun Wong

IPC: G11C16/08 ,  B41J2/045 ,  G11C16/32

CPC classification number: B41J2/04541 ,  B41J2/04543 ,  B41J2/0458 ,  B41J2/04581 ,  B41J2/04586 ,  G11C16/08 ,  G11C16/32

Abstract: Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a plurality of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the plurality of cells. A column shift register is coupled to the column select ports of the plurality of cells, the column shift register having a register location for each column of the plurality of cells and having an input to receive a first input signal. A row shift register is coupled to row select ports of the plurality of cells, the row shift register having a register location for each row of the plurality of cells and having an input to receive a second input signal.

公开(公告)号：US10224935B2

公开(公告)日：2019-03-05

申请号：US15520698

申请日：2014-10-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Ning Ge ,  Boon Bing Ng ,  Leong Yap Chia

IPC: H03K19/18 ,  H03K19/173 ,  H03K3/45 ,  H03K19/0944 ,  G11C13/00

Abstract: A device having ratioed logic with a high impedance load is described. The device includes a pull-down network coupled between a first voltage and an output. The device also includes a high impedance load coupled between a second voltage and the output. The high impedance load being smaller than a transistor of the pull-down network.

公开(公告)号：US20180134037A1

公开(公告)日：2018-05-17

申请号：US15558618

申请日：2015-07-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Wai Mun Wong ,  Leong Yap Chia ,  Ning Ge

IPC: B41J2/05 ,  B41J2/14 ,  B41J2/16

CPC classification number: B41J2/05 ,  B41J2/14072 ,  B41J2/14129 ,  B41J2/16 ,  B41J2202/03 ,  B41J2202/11

Abstract: The present subject matter relates to a printhead assembly comprising a plurality of print nozzles in a nozzle array. Each of the plurality of print nozzles is coupled to a printhead firing resistor, the printhead firing resistor being individually addressable. A print control circuit is to actuate the printhead firing resistor. In accordance with one example implementation of the present subject matter, the print control circuit comprises pull-down resistors made of Tantalum-Aluminum (Ta—Al).

公开(公告)号：US20170317680A1

公开(公告)日：2017-11-02

申请号：US15520698

申请日：2014-10-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Ning Ge ,  Boon Bing Ng ,  Leong Yap Chia

IPC: H03K19/18 ,  H03K19/0944

CPC classification number: H03K19/18 ,  G11C13/0002 ,  H03K3/45 ,  H03K19/0944 ,  H03K19/173

Abstract: A device having ratioed logic with a high impedance load is described. The device includes a pull-down network coupled between a first voltage and an output. The device also includes a high impedance load coupled between a second voltage and the output. The high impedance load being smaller than a transistor of the pull-down network.

公开(公告)号：US09786777B2

公开(公告)日：2017-10-10

申请号：US14913980

申请日：2013-08-30

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Ning Ge ,  Leong Yap Chia ,  Pin Chin Lee ,  Jose Jehrome Rando

IPC: H01L21/00 ,  H01L29/74 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L29/66575 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/78 ,  H05K2203/013

Abstract: A semiconductor device and method of forming the same is described. In an example, a polysilicon layer is deposited on a substrate having at least one polysilicon ring. The substrate is doped using the polysilicon layer as a mask to form doped regions in the substrate. A dielectric layer is deposited over the polysilicon layer and the substrate. The dielectric layer is etched to expose portions of the polysilicon layer. A metal layer is deposited on the dielectric layer. The metal layer, the dielectric layer, and the exposed portions of the polysilicon layer are etched such that at least a portion of each polysilicon ring is removed.

公开(公告)号：US10224335B2

公开(公告)日：2019-03-05

申请号：US15541986

申请日：2015-01-29

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Wai Mun Wong ,  Leong Yap Chia ,  Ning Ge

IPC: H01L29/49 ,  H01L27/11521 ,  H01L27/1156 ,  G11C16/04

Abstract: The present subject matter relates to an integrated circuit comprising an erasable programmable read only memory (EPROM) array having a plurality of EPROM cells disposed in rows and columns, wherein one or more EPROM cells located at predetermined positions in the EPROM array are selectively dischargeable. The one or more EPROM cells comprise a EPROM transistor having a first conductive layer to store electrons upon the EPROM transistor being programmed and a control metal oxide semiconductor field-effect transistor (MOSFET) electrically connected to the first conductive layer to provide an electron leakage path to dissipate the electrons stored in the first conductive layer in a predetermined leak time period.

公开(公告)号：US09987842B2

公开(公告)日：2018-06-05

申请号：US15518934

申请日：2014-10-29

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Jianwen Luo ,  Leong Yap Chia ,  Ning Ge

IPC: B41J2/045 ,  B41J2/175

CPC classification number: B41J2/04541 ,  B41J2/0458 ,  B41J2/04581 ,  B41J2/1753 ,  B41J2/17546 ,  B41J2202/17

Abstract: A print head with a number of memristors and inverters is described. The print head includes a number of nozzles to deposit an amount of fluid onto a print medium. Each nozzle includes a firing chamber to hold the amount of fluid, an opening to dispense the amount of fluid onto the print medium, and an ejector to eject the amount of fluid through the opening. The print head also includes a number of memristor cells. Each memristor cell includes a memristor to store data, a voltage divider serially connected to the 116 memristor cell, and an inverter connected in parallel with the number of memristor cells and the voltage divider.