公开(公告)号：US20220276788A1

公开(公告)日：2022-09-01

申请号：US17746652

申请日：2022-05-17

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yongyao LI ,  Guoyu WANG ,  Jun YU ,  You LI ,  Jiawu LIU

IPC: G06F3/06

Abstract: This application provides a method for detecting margins of a data signal. A receive end of a data signal may adjust a voltage of a reference power source; adjust, based on a plurality of reference moments included in a reference moment set, a moment of an edge of a data strobe signal transmitted by a transmit end of the data signal; and during the adjustment, for each reference voltage and each reference moment, determine whether a bit error exists in data obtained by decoding the data signal when the voltage of the reference power source is the reference voltage and the moment of the edge of the data strobe signal is the reference moment, to obtain a timing margin of the data signal at each reference voltage and a voltage margin of the data signal at each reference moment.

公开(公告)号：US20220330417A1

公开(公告)日：2022-10-13

申请号：US17852581

申请日：2022-06-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yongyao LI ,  Shibin XU ,  Wei KANG ,  Feng WANG ,  Xue FENG ,  Jiang ZHU

IPC: H05K1/02 ,  H05K3/34

Abstract: This application provides an electronic module and an electronic device. The electronic module includes a first component, a second component, and a plurality of terminals. The first component includes a package substrate and a chip mounted on the package substrate. The second component includes a circuit board and a mount base mounted on the circuit board. Each terminal includes a body part, and a first bent part and a solder ball that are respectively connected to two opposite ends of the body part. In each terminal, the body part passes through and is fastened to the mount base, the first bent part presses against a corresponding first solder pad on the package substrate, and the solder ball is connected to a corresponding second solder pad on the circuit board.

公开(公告)号：US20210297228A1

公开(公告)日：2021-09-23

申请号：US17321707

申请日：2021-05-17

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yongyao LI ,  Fei LUO ,  Jiankang LI ,  Jiang ZHU ,  Jieping ZENG

IPC: H04L7/00 ,  G06F13/42

Abstract: This application provides a drive and a data transmission method, to implement low-latency transmission. The drive includes a CDR circuit, an elastic buffer, a receiver circuit, and a transmitter circuit. The CDR circuit is configured to recover a receive clock from a received signal. The receiver circuit is configured to recover sent data from the received signal by using the receive clock. The elastic buffer is configured to move the sent data in by using the receive clock and move the data out by using the receive clock. The transmitter circuit is configured to send the sent data from the elastic buffer by using the receive clock.

公开(公告)号：US20210075647A1

公开(公告)日：2021-03-11

申请号：US17100033

申请日：2020-11-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yongyao LI ,  Fei LUO ,  Er NIE

IPC: H04L25/03 ,  H04B1/38 ,  G06F13/42

Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.