公开(公告)号：US20160172483A1

公开(公告)日：2016-06-16

申请号：US14853459

申请日：2015-09-14

Applicant: HYUNDAI MOTOR COMPANY

Inventor： Dae Hwan CHUN ,  Jong Seok LEE ,  Junghee PARK ,  Kyoung-Kook HONG ,  Youngkyun JUNG

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66719

Abstract: The present inventive concept relates to a semiconductor device, and more particularly to a semiconductor device that can increase the amount of current by reducing impedance, and a method of manufacturing the semiconductor device.A semiconductor device comprises an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; an n+ region disposed on the n− type epitaxial layer; first and second trenches disposed in the n− type epitaxial layer and the n+ region; first and second gate insulating layers disposed inside the first and second trenches, respectively; first and second gate electrodes disposed on the first and second gate insulating layers, respectively; a p-type region disposed on two sides of one of the first and second trenches; an oxidation film diposed on the first and second gate electrodes; a source electrode disposed on the n+ region and the oxidation film; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein a first channel is disposed on two sides of the first trench and a second channel is disposed on two sides of the second trench.

Abstract translation: 本发明构思涉及一种半导体器件，更具体地，涉及一种可以通过减少阻抗来增加电流量的半导体器件，以及制造半导体器件的方法。 半导体器件包括设置在n +型碳化硅衬底的第一表面上的n型外延层; 设置在n型外延层上的n +区; 设置在n型外延层和n +区域中的第一和第二沟槽; 分别设置在第一和第二沟槽内的第一和第二栅极绝缘层; 分别设置在第一和第二栅极绝缘层上的第一和第二栅极电极; 设置在所述第一和第二沟槽中的一个的两侧上的p型区域; 浸渍在第一和第二栅电极上的氧化膜; 设置在n +区域上的源电极和氧化膜; 以及设置在所述n +型碳化硅衬底的第二表面上的漏电极，其中第一通道设置在所述第一沟槽的两侧，而第二沟道设置在所述第二沟槽的两侧。

公开(公告)号：US20140183560A1

公开(公告)日：2014-07-03

申请号：US14104974

申请日：2013-12-12

Applicant: Hyundai Motor Company

Inventor： Jong Seok LEE ,  Kyoung-Kook HONG ,  Dae Hwan CHUN ,  Youngkyun JUNG

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7813

Abstract: A semiconductor device includes an n+ type silicon carbide substrate; a plurality of n type pillar regions, a plurality of p type pillar regions, and an n− type epitaxial layer disposed on a first surface of the n+ type silicon carbide substrate; a p type epitaxial layer and an n+ region sequentially disposed on the n− type epitaxial layer; a trench penetrating the n+ region and the p type epitaxial layer and disposed on the n− type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode positioned on a second surface of the n+ type silicon carbide substrate.

Abstract translation: 半导体器件包括n +型碳化硅衬底; 设置在n +型碳化硅衬底的第一表面上的多个n型支柱区域，多个p型支柱区域和n型外延层; 顺序地设置在n型外延层上的p型外延层和n +区; 穿过n +区和p型外延层并设置在n型外延层上的沟槽; 设置在所述沟槽内的栅极绝缘膜; 设置在所述栅极绝缘膜上的栅电极; 设置在栅电极上的氧化膜; 设置在p型外延层上的源电极，n +区和氧化膜; 以及位于n +型碳化硅衬底的第二表面上的漏电极。

公开(公告)号：US20140183559A1

公开(公告)日：2014-07-03

申请号：US14098409

申请日：2013-12-05

Applicant: Hyundai Motor Company

Inventor： Jong Seok LEE ,  Kyoung-Kook HONG ,  Dae Hwan CHUN ,  Youngkyun JUNG

IPC: H01L29/16 ,  H01L21/04 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1608 ,  H01L21/0455 ,  H01L29/0623 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7813

Abstract: The present inventive concept has been made in an effort to improve the breakdown voltage of a silicon carbide MOSFET using a trench gate.A semiconductor device according to the present inventive concept includes a p type pillar region disposed below the trench, spaced apart from the trench or a first p type pillar region and a second p type pillar region disposed below the trench and corresponding to two corners of the trench.

Abstract translation: 本发明构思是为了改善使用沟槽栅极的碳化硅MOSFET的击穿电压。 根据本发明构思的半导体器件包括设置在沟槽下方的与沟槽间隔开的p型柱状区域或设置在沟槽下方并对应于沟槽的两个角的第一p型柱状区域和第二p型支柱区域 。

公开(公告)号：US20140183557A1

公开(公告)日：2014-07-03

申请号：US14092098

申请日：2013-11-27

Applicant: HYUNDAI MOTOR COMPANY

Inventor： Su Bin KANG ,  Kyoung-Kook HONG ,  Jong Seok LEE ,  Youngkyun JUNG

IPC: H01L29/45 ,  H01L21/28 ,  H01L29/16

CPC classification number: H01L29/45 ,  H01L21/0485 ,  H01L29/1608

Abstract: A semiconductor device structure for an ohmic contact is provided, including a silicon carbide substrate and an ohmic contact layer disposed on the silicon carbide substrate. A carbon layer is disposed on the ohmic contact layer. An anti-diffusion layer is disposed on the carbon layer, and a pad layer is disposed on the anti-diffusion layer. The anti-diffusion layer is made of any one of tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

Abstract translation: 提供了一种用于欧姆接触的半导体器件结构，包括碳化硅衬底和设置在碳化硅衬底上的欧姆接触层。 碳层设置在欧姆接触层上。 在碳层上设置防扩散层，在反扩散层上设置衬垫层。 抗扩散层由钨（W），钛（Ti），氮化钛（TiN），钽（Ta）和氮化钽（TaN）中的任一种制成。

公开(公告)号：US20140167072A1

公开(公告)日：2014-06-19

申请号：US14095650

申请日：2013-12-03

Applicant: Hyundai Motor Company

Inventor： Dae Hwan CHUN ,  Jong Seok LEE ,  Kyoung-Kook HONG ,  Youngkyun JUNG

IPC: H01L29/872 ,  H01L29/66

CPC classification number: H01L29/872 ,  H01L29/1608 ,  H01L29/66143 ,  H01L29/8611

Abstract: A schottky barrier diode includes an n− type epitaxial layer disposed at a first surface of an n+ type silicon carbide substrate, a plurality of n type pillar areas disposed in the n− type epitaxial layer at a first portion of a first surface of the n+ type silicon carbide substrate, a plurality of p+ areas disposed at a surface of the n− type epitaxial layer and separated from the n type pillar area, a schottky electrode disposed on the n− type epitaxial layer and the p+ area, and an ohmic electrode disposed at a second surface of the n+ type silicon carbide substrate. A doping density of the n type pillar area is larger than a doping density of the n− type epitaxial layer.

Abstract translation: 肖特基势垒二极管包括设置在n +型碳化硅衬底的第一表面上的n型外延层，在n +型碳化硅衬底的第一表面的第一部分处设置在n型外延层中的多个n型衬底区域， 配置在n型外延层的表面并与n型支柱区分离的多个p +区域，设置在n型外延层和p +区域上的肖特基电极以及欧姆电极 设置在n +型碳化硅衬底的第二表面。 n型支柱区域的掺杂密度大于n型外延层的掺杂密度。