SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号:US20160172483A1

    公开(公告)日:2016-06-16

    申请号:US14853459

    申请日:2015-09-14

    CPC classification number: H01L29/7813 H01L29/1608 H01L29/66068 H01L29/66719

    Abstract: The present inventive concept relates to a semiconductor device, and more particularly to a semiconductor device that can increase the amount of current by reducing impedance, and a method of manufacturing the semiconductor device.A semiconductor device comprises an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; an n+ region disposed on the n− type epitaxial layer; first and second trenches disposed in the n− type epitaxial layer and the n+ region; first and second gate insulating layers disposed inside the first and second trenches, respectively; first and second gate electrodes disposed on the first and second gate insulating layers, respectively; a p-type region disposed on two sides of one of the first and second trenches; an oxidation film diposed on the first and second gate electrodes; a source electrode disposed on the n+ region and the oxidation film; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein a first channel is disposed on two sides of the first trench and a second channel is disposed on two sides of the second trench.

    Abstract translation: 本发明构思涉及一种半导体器件,更具体地,涉及一种可以通过减少阻抗来增加电流量的半导体器件,以及制造半导体器件的方法。 半导体器件包括设置在n +型碳化硅衬底的第一表面上的n型外延层; 设置在n型外延层上的n +区; 设置在n型外延层和n +区域中的第一和第二沟槽; 分别设置在第一和第二沟槽内的第一和第二栅极绝缘层; 分别设置在第一和第二栅极绝缘层上的第一和第二栅极电极; 设置在所述第一和第二沟槽中的一个的两侧上的p型区域; 浸渍在第一和第二栅电极上的氧化膜; 设置在n +区域上的源电极和氧化膜; 以及设置在所述n +型碳化硅衬底的第二表面上的漏电极,其中第一通道设置在所述第一沟槽的两侧,而第二沟道设置在所述第二沟槽的两侧。

Patent Agency Ranking