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公开(公告)号：US20130019085A1
公开(公告)日：2013-01-17
申请号：US13180634
申请日：2011-07-12
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3804 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3859 , G06F9/3861
摘要： A mechanism is provided for reducing a penalty for executing a correct branch of a branch instruction. An execution unit in a processor of a data processing system executes a first branch of the branch instruction from a main thread of a processor and executes a second branch of the branch instruction from an assist thread of the processor. The execution unit determines whether the main thread is a correct branch of the branch instruction or the assist thread is the correct branch of the branch instruction. Responsive to the assist thread being the correct branch of the branch instruction, the execution unit pauses execution of the branch instruction on both the main thread and the assist thread. The execution unit then properly inherits a context of the main thread in order that execution of the second branch may continue.
摘要翻译： 提供了用于减少执行分支指令的正确分支的惩罚的机制。 数据处理系统的处理器中的执行单元从处理器的主线程执行分支指令的第一分支，并从处理器的辅助线程执行分支指令的第二分支。 执行单元确定主线程是否是分支指令的正确分支，或辅助线程是分支指令的正确分支。 响应于辅助线程是分支指令的正确分支，执行单元暂停在主线程和辅助线程上执行分支指令。 执行单元然后适当地继承主线程的上下文，以便第二分支的执行可以继续。
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公开(公告)号：US20130019083A1
公开(公告)日：2013-01-17
申请号：US13179672
申请日：2011-07-11
申请人： Harold W. Cain, III , David M. Daly , Kattamuri Ekanadham , Michael C. Huang , Jose E. Moreira , Mauricio J. Serrano
发明人： Harold W. Cain, III , David M. Daly , Kattamuri Ekanadham , Michael C. Huang , Jose E. Moreira , Mauricio J. Serrano
IPC分类号： G06F9/30
CPC分类号： G06F9/30087 , G06F9/3834 , G06F9/3842 , G06F11/1492 , G06F11/1629 , G06F2201/845
摘要： A mechanism is provided for redundant execution of a set of instructions. A redundant execution begin (rbegin) instruction to be executed by a first hardware thread on the first processor is identified in the set of instructions. The set of instructions immediately after the rbegin instruction are executed on the first hardware thread and on a second hardware thread. Responsive to both the first processor and the second processor ending execution of the set of instructions, responsive to a first set of cache lines in a first speculative store matching a second set of cache lines in a second speculative store, and responsive to a first set of register states in a first status register matching a second set of register states in a second status register, dirty lines in the first speculative store are committed thereby committing a redundant transaction state to an architectural state.
摘要翻译： 提供了用于一组指令的冗余执行的机制。 在该组指令中识别由第一处理器上的第一硬件线程执行的冗余执行开始（rbegin）指令。 rbegin指令之后的指令集在第一个硬件线程和第二个硬件线程上执行。 响应于所述第一处理器和所述第二处理器结束所述指令集的执行，响应于在第二推测存储器中匹配第二组高速缓存行的第一推测存储器中的第一组高速缓存行，并响应于第一集合 在与第二状态寄存器中的第二组寄存器状态匹配的第一状态寄存器中的寄存器状态被提交，从而将第一推测存储器中的脏线提交给架构状态的冗余事务状态。
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公开(公告)号：US08255626B2
公开(公告)日：2012-08-28
申请号：US12633906
申请日：2009-12-09
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30181 , G06F9/3842 , G06F9/3857 , G06F9/467
摘要： Mechanisms for performing predicated atomic commits based on consistency of watches is provided. These mechanisms include executing, by a thread executing on a processor of the data processing system, an atomic release instruction. A determination is made as to whether a speculative store has been lost, due to an eviction of a memory block to which the speculative store is performed, since a previous atomic release instruction was processed. In response to the speculative store having been lost, invalidating, by the processor, speculative stores that have been performed since the previous atomic release instruction was processed. In addition, the method comprises, in response to the speculative store not having been lost, committing, by the processor, speculative stores that have been performed since the previous atomic release instruction was processed.
摘要翻译： 提供了基于手表一致性执行预定原子提交的机制。 这些机制包括通过在数据处理系统的处理器上执行的线程执行原子释放指令。 自从先前的原子释放指令被处理以来，确定推测存储是否由于执行了推测性存储的存储块的驱逐而丢失。 响应于投机存储已经丢失，由处理器使得自从先前的原子释放指令被处理以来已经执行的推测存储器无效。 此外，该方法响应于推测存储没有丢失，由处理器提交自从先前的原子释放指令被处理以来已经执行的推测存储。
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公开(公告)号：US20110066820A1
公开(公告)日：2011-03-17
申请号：US12559615
申请日：2009-09-15
IPC分类号： G06F12/02
CPC分类号： G06F9/3842 , G06F9/3824
摘要： A method, a system and a computer program product for handling speculative stores. The system determines when a speculative store buffer is not full. An indicator is generated when the speculative store buffer is not full, and the speculative stores are input into the speculative store buffer. When the speculative store buffer is full, a full buffer indicator is generated. Speculative stores prevented from entering the speculative store buffer are overflow stores. The overflow list is searched to determine whether one or more addresses of the overflow stores are present in the overflow list. When one or more addresses of the overflow stores are not present in the overflow list, the overflow stores are stored in the overflow list.
摘要翻译： 一种用于处理投机店的方法，系统和计算机程序产品。 系统确定推测存储缓冲区何时未满。 当推测存储缓冲区未满时，生成指示符，并将推测存储输入到推测存储缓冲区。 当推测性存储缓冲区已满时，将生成完整的缓冲区指示符。 防止进入推测存储缓冲区的推测存储是溢出存储。 搜索溢出列表以确定溢出列表中是否存在溢出存储的一个或多个地址。 当溢出列表中不存在溢出存储的一个或多个地址时，溢出存储将存储在溢出列表中。
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公开(公告)号：US20110016470A1
公开(公告)日：2011-01-20
申请号：US12504925
申请日：2009-07-17
IPC分类号： G06F9/46
CPC分类号： G06F9/528
摘要： Mechanisms are provided for handling conflicts in a transactional memory system. The mechanisms execute threads in a data processing system in a first conflict resolution mode of operation in which threads execute conflicting transactional blocks speculatively. The mechanisms determine, for a transactional block, if the first conflict resolution mode of operation is to be transitioned to a second conflict resolution mode of operation in which threads accessing conflicting transactional blocks are executed serially and non-speculatively. Moreover, the mechanisms execute a thread that accesses the transactional block using the second conflict resolution mode of operation in response to the determination indicating that the first conflict resolution mode of operation is to be transitioned to the second conflict resolution mode of operation.
摘要翻译： 提供了用于处理事务性存储系统中的冲突的机制。 这些机制在第一冲突解决操作模式下在数据处理系统中执行线程，其中线程以推测方式执行冲突的事务块。 这些机制为事务块确定是否将第一冲突解决方案的操作转变为第二冲突解决操作模式，其中访问冲突事务块的线程被串行和非推测地执行。 此外，机制响应于指示第一冲突解决方案操作被转换到第二冲突解决操作模式的确定，执行使用第二冲突解决操作模式访问事务块的线程。
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公开(公告)号：US20110066831A1
公开(公告)日：2011-03-17
申请号：US12559643
申请日：2009-09-15
IPC分类号： G06F9/30
CPC分类号： G06F9/30076 , G06F11/1407
摘要： A method, system and computer program product for issuing one or more software initiated operations for creating a checkpoint of a register file and memory, and for restoring a register file and memory to the checkpointed state. At the execution of a checkpoint operation, the system returns a condition code indicating success or failure. When the condition code is set equal to one, one or more checkpoints are initiated. Contents of the register file and gated store buffer are stored each time the one or more checkpoints are initiated. When the checkpoint is created, the system notifies software when a hardware checkpoint capacity has been reached. One or more of the software checkpoint, hardware checkpoint, and handler checkpoint are utilized to provide a more precise point of restoration. During software execution, the register file and gated store buffer can be restored as defined by the one or more previous checkpoints.
摘要翻译： 一种方法，系统和计算机程序产品，用于发出用于创建寄存器文件和存储器的检查点的一个或多个软件发起的操作，以及用于将寄存器文件和存储器恢复到检查点状态。 在执行检查点操作时，系统返回指示成功或失败的条件代码。 当条件代码设置为等于1时，将启动一个或多个检查点。 每次启动一个或多个检查点时，都会存储寄存器文件和门控存储缓冲区的内容。 当检查点创建时，系统在达到硬件检查点容量时通知软件。 利用一个或多个软件检查点，硬件检查点和处理程序检查点来提供更精确的恢复点。 在软件执行期间，寄存器文件和门控存储缓冲区可以由一个或多个以前的检查点定义来恢复。
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17.发明授权公开(公告)号：US08539486B2
公开(公告)日：2013-09-17
申请号：US12504925
申请日：2009-07-17
CPC分类号： G06F9/528
摘要： Mechanisms are provided for handling conflicts in a transactional memory system. The mechanisms execute threads in a data processing system in a first conflict resolution mode of operation in which threads execute conflicting transactional blocks speculatively. The mechanisms determine, for a transactional block, if the first conflict resolution mode of operation is to be transitioned to a second conflict resolution mode of operation in which threads accessing conflicting transactional blocks are executed serially and non-speculatively. Moreover, the mechanisms execute a thread that accesses the transactional block using the second conflict resolution mode of operation in response to the determination indicating that the first conflict resolution mode of operation is to be transitioned to the second conflict resolution mode of operation.
摘要翻译： 提供了用于处理事务性存储系统中的冲突的机制。 这些机制在第一冲突解决操作模式下在数据处理系统中执行线程，其中线程以推测方式执行冲突的事务块。 这些机制为事务块确定是否将第一冲突解决方案的操作转变为第二冲突解决操作模式，其中访问冲突事务块的线程被串行和非推测地执行。 此外，机制响应于指示第一冲突解决方案操作被转换到第二冲突解决操作模式的确定，执行使用第二冲突解决操作模式访问事务块的线程。
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公开(公告)号：US20110138126A1
公开(公告)日：2011-06-09
申请号：US12633906
申请日：2009-12-09
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30181 , G06F9/3842 , G06F9/3857 , G06F9/467
摘要： Mechanisms for performing predicated atomic commits based on consistency of watches is provided. These mechanisms include executing, by a thread executing on a processor of the data processing system, an atomic release instruction. A determination is made as to whether a speculative store has been lost, due to an eviction of a memory block to which the speculative store is performed, since a previous atomic release instruction was processed. In response to the speculative store having been lost, invalidating, by the processor, speculative stores that have been performed since the previous atomic release instruction was processed. In addition, the method comprises, in response to the speculative store not having been lost, committing, by the processor, speculative stores that have been performed since the previous atomic release instruction was processed.
摘要翻译： 提供了基于手表一致性执行预定原子提交的机制。 这些机制包括通过在数据处理系统的处理器上执行的线程执行原子释放指令。 自从先前的原子释放指令被处理以来，确定推测存储是否由于执行了推测性存储的存储块的驱逐而丢失。 响应于投机存储已经丢失，由处理器使得自从先前的原子释放指令被处理以来已经执行的推测存储器无效。 此外，该方法响应于推测存储没有丢失，由处理器提交自从先前的原子释放指令被处理以来已经执行的推测存储。
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公开(公告)号：US20120331233A1
公开(公告)日：2012-12-27
申请号：US13167773
申请日：2011-06-24
IPC分类号： G06F12/08
CPC分类号： G06F12/0815
摘要： A mechanism is provided for detecting false sharing misses. Responsive to performing either an eviction or an invalidation of a cache line in a cache memory of the data processing system, a determination is made as to whether there is an entry associated with the cache line in a false sharing detection table. Responsive to the entry associated with the cache line existing in the false sharing detection table, a determination is made as to whether an overlap field associated with the entry is set. Responsive to the overlap field failing to be set, identification is made that a false sharing coherence miss has occurred. A first signal is then sent to a performance monitoring unit indicating the false sharing coherence miss.
摘要翻译： 提供了一种检测虚假共享漏洞的机制。 响应于执行数据处理系统的高速缓冲存储器中的高速缓存行的驱逐或无效，在虚假共享检测表中确定是否存在与高速缓存行相关联的条目。 响应于与虚假共享检测表中存在的高速缓存行相关联的条目，确定是否设置与条目相关联的重叠字段。 响应于重叠字段未能设置，识别出发生错误共享一致性错误。 然后，第一信号被发送到指示虚假共享一致性丢失的性能监视单元。
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公开(公告)号：US09058270B2
公开(公告)日：2015-06-16
申请号：US13167773
申请日：2011-06-24
CPC分类号： G06F12/0815
摘要： A mechanism is provided for detecting false sharing misses. Responsive to performing either an eviction or an invalidation of a cache line in a cache memory of the data processing system, a determination is made as to whether there is an entry associated with the cache line in a false sharing detection table. Responsive to the entry associated with the cache line existing in the false sharing detection table, a determination is made as to whether an overlap field associated with the entry is set. Responsive to the overlap field failing to be set, identification is made that a false sharing coherence miss has occurred. A first signal is then sent to a performance monitoring unit indicating the false sharing coherence miss.
摘要翻译： 提供了一种检测虚假共享漏洞的机制。 响应于执行数据处理系统的高速缓冲存储器中的高速缓存行的驱逐或无效，在虚假共享检测表中确定是否存在与高速缓存行相关联的条目。 响应于与虚假共享检测表中存在的高速缓存行相关联的条目，确定是否设置与条目相关联的重叠字段。 响应于重叠字段未能设置，识别出发生错误共享一致性错误。 然后，第一信号被发送到指示虚假共享一致性丢失的性能监视单元。
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