公开(公告)号：US20110314259A1

公开(公告)日：2011-12-22

申请号：US12817609

申请日：2010-06-17

申请人： Kattamuri Ekanadham ,  Brian R. Konigsburg ,  David S. Levitan ,  Jose E. Moreira ,  David Mui ,  IL Park

发明人： Kattamuri Ekanadham ,  Brian R. Konigsburg ,  David S. Levitan ,  Jose E. Moreira ,  David Mui ,  IL Park

IPC分类号： G06F9/30

CPC分类号： G06F9/30 ,  G06F9/30134 ,  G06F9/30163 ,  G06F9/3861

摘要： A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.

摘要翻译： 一个指针用于指向一堆信息中的下一个读取位置。 将信息推送到堆栈中：保存指针的值，该指针指向堆栈内的第一个位置作为下一个读取位置; 指针被更新，使得它指向堆栈内的第二位置作为下一个读取位置; 并且将信息写入第二位置处的存储。 为了从堆栈弹出信息：响应于指针，从第二位置读取信息作为下一个读取位置; 并且指针被恢复为等于保存的值，使得其指向作为下一个读取位置的第一位置。

公开(公告)号：US20100287536A1

公开(公告)日：2010-11-11

申请号：US12436894

申请日：2009-05-07

申请人： I-Hsin Chung ,  Guojing Cong ,  Kattamuri Ekanadham ,  David Klepacki ,  Simone Sbaraglia ,  Hui-Fang Wen

发明人： I-Hsin Chung ,  Guojing Cong ,  Kattamuri Ekanadham ,  David Klepacki ,  Simone Sbaraglia ,  Hui-Fang Wen

IPC分类号： G06F11/36 ,  G06F9/44 ,  G06F9/45

CPC分类号： G06F8/443 ,  G06F11/3471 ,  G06F2201/865

摘要： During runtime of a binary program file, streams of instructions are executed and memory references, generated by instrumentation applied to given ones of the instructions that refer to memory locations, are collected. A transformation is performed, based on the executed streams of instructions and the collected memory references, to obtain a table. The table lists memory events of interest for active data structures for each function in the program file. The transformation is performed to translate memory addresses for given ones of the instructions and given ones of the data structures into locations and variable names in a source file corresponding to the binary file. At least the memory events of interest are displayed, and the display is organized so as to correlate the memory events of interest with corresponding ones of the data structures.

摘要翻译： 在二进制程序文件的运行期间，执行指令流，并且收集通过应用于指向存储器位置的给定指令的仪器产生的存储器引用。 基于所执行的指令流和所收集的存储器引用执行变换以获得表。 该表列出了程序文件中每个功能的活动数据结构感兴趣的内存事件。 执行转换以将给定的指令的内存地址转换为与二进制文件相对应的源文件中的数据结构中的位置和变量名。 至少显示感兴趣的存储器事件，并且显示被组织以使感兴趣的存储器事件与相应的数据结构相关联。

公开(公告)号：US06085295A

公开(公告)日：2000-07-04

申请号：US954496

申请日：1997-10-20

申请人： Kattamuri Ekanadham ,  Beng-Hong Lim ,  Pratap Chandra Pattnaik ,  Marc Snir

发明人： Kattamuri Ekanadham ,  Beng-Hong Lim ,  Pratap Chandra Pattnaik ,  Marc Snir

IPC分类号： G06F12/08 ,  G06F12/16

CPC分类号： G06F12/0813 ,  G06F12/0817 ,  G06F2212/2542

摘要： A method of providing coherent shared memory access among a plurality of shared memory multiprocessor nodes. For each line of data in each of the nodes, a list of those processors of the node that have copies of the line in their caches is maintained. If a memory command is issued from a processor of one node, and if the command is directed to a line of memory of another node, then the memory command is sent directly to an adapter of the one node. When the adapter receives the command, it forwards the command from the one adapter to another adapter of the other node. When the other adapter receives the command, the command is forwarded to the local memory of the other node. The list of processors is then updated in the local memory of the other node to include or exclude the other adapter depending on the command. If the memory command is issued from one of the processors of one of the nodes, and if the command is directed to a line of memory of the one node, then the command is sent directly to local memory. When the local memory receives the command and if the adapter of the node is in the list of processors for a line associated with the command and if the command is a write command, then the command is forwarded to the adapter of the one node. When the adapter receives the command, the command is forwarded to remote adapters in each of the remote nodes which have processors which have cache copies of the line. Finally, when the latter remote adapters receive the command, the command is forwarded to the processors having the cache copies of the line.

摘要翻译： 一种在多个共享存储器多处理器节点之间提供一致的共享存储器访问的方法。 对于每个节点中的每一行数据，维护节点中具有其高速缓存中的行的副本的那些处理器的列表。 如果从一个节点的处理器发出存储器命令，并且如果命令被定向到另一个节点的存储器行，则存储器命令被直接发送到该一个节点的适配器。 当适配器接收到命令时，它将该命令从一个适配器转发到另一个节点的另一个适配器。 当另一个适配器接收到该命令时，该命令将转发到另一个节点的本地内存。 然后在另一个节点的本地存储器中更新处理器列表，以根据命令包括或排除另一个适配器。 如果从其中一个节点的一个处理器发出存储器命令，并且如果命令被定向到一个节点的存储器行，则该命令被直接发送到本地存储器。 当本地内存接收到该命令时，如果节点的适配器位于与该命令相关联的一行的处理器列表中，并且该命令是写入命令，则该命令将转发到该一个节点的适配器。 当适配器接收到该命令时，该命令将转发到具有具有该行的高速缓存副本的处理器的每个远程节点中的远程适配器。 最后，当后一个远程适配器接收到该命令时，该命令被转发到具有该行的缓存副本的处理器。

公开(公告)号：US5408658A

公开(公告)日：1995-04-18

申请号：US730365

申请日：1991-07-15

申请人： Rudolph N. Rechtschaffen ,  Kattamuri Ekanadham

发明人： Rudolph N. Rechtschaffen ,  Kattamuri Ekanadham

IPC分类号： G06F9/38 ,  G06F9/45 ,  G06F15/16

CPC分类号： G06F9/3808 ,  G06F8/451 ,  G06F9/3802 ,  G06F9/3812 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857

摘要： An incremental method is described for distributing the instructions of an execution sequence among a plurality of processing elements for execution in parallel. The distribution is based upon anticipated availability times of the needed input values for each instruction as well as the anticipated availability times of each processing element for handling each instruction. A self-parallelizing computer system and method are also described for asynchronously processing the distributed instructions in two modes of execution on a set of processing elements which communicate with each other.

摘要翻译： 描述了用于在多个处理元件之间并行执行执行序列的指令的分发方法。 该分配基于每个指令的所需输入值的预期可用时间以及用于处理每个指令的每个处理元件的预期可用时间。 还描述了一种自并行计算机系统和方法，用于在一组彼此通信的处理元件上以两种执行模式异步处理分布式指令。

公开(公告)号：US20120239904A1

公开(公告)日：2012-09-20

申请号：US13048214

申请日：2011-03-15

申请人： Kattamuri Ekanadham ,  Hung Q. Le ,  Jose E. Moreira ,  Pratap C. Pattnaik

发明人： Kattamuri Ekanadham ,  Hung Q. Le ,  Jose E. Moreira ,  Pratap C. Pattnaik

IPC分类号： G06F9/30 ,  G06F12/10

CPC分类号： G06F9/3877 ,  G06F9/30043 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3851 ,  G06F12/1027

摘要： A method, system and computer program product are disclosed for interfacing between a multi-threaded processing core and an accelerator. In one embodiment, the method comprises copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core, and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads. Whenever any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for the any one of the threads. This facilitates starting that specified operation without memory translation faults. In an embodiment, the copying includes, each time one of the memory address translations is updated on the processing core, copying the updated one of the memory address translations to the hardware accelerator.

摘要翻译： 公开了用于在多线程处理核心和加速器之间进行接口的方法，系统和计算机程序产品。 在一个实施例中，该方法包括从处理核心复制到在处理核心上操作的多个线程中的每个线程的硬件加速器存储器地址转换，以及同时在硬件加速器上存储每个线程的一个或多个存储器地址转换 。 只要在处理核心上操作的多个线程中的任何一个指示硬件加速器执行指定的操作，则硬件加速器在其上存储有针对任何一个线程的一个或多个存储器地址转换。 这有助于启动指定的操作而不会出现内存转换错误 在一个实施例中，复制包括每次在处理核心上更新一个存储器地址转换时，将更新的一个存储器地址转换复制到硬件加速器。

公开(公告)号：US20110138101A1

公开(公告)日：2011-06-09

申请号：US12633428

申请日：2009-12-08

申请人： Kattamuri Ekanadham ,  Il Park ,  Pratap Pattnaik

发明人： Kattamuri Ekanadham ,  Il Park ,  Pratap Pattnaik

IPC分类号： G06F12/06

CPC分类号： G06F9/30007 ,  G06F12/0817 ,  G06F12/1027

摘要： A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain.

摘要翻译： 公开了用于维持数据一致性的方法，系统和计算机程序产品，用于多节点处理系统，其中每个节点包括一个或多个组件。 在一个实施例中，该方法包括建立数据域，将一组组件分配给数据域，将相干消息从处理系统的第一组件发送到处理系统的第二组件，以及确定该第二组件 被分配给数据域。 在该实施例中，如果该第二组件被分配给数据域，则将相干消息传送到分配给数据域的所有组件，以维持这些组件之间的数据一致性。 在一个实施例中，如果将该第二组件分配给数据域，则将第一组件分配给数据域。

公开(公告)号：US20090216956A1

公开(公告)日：2009-08-27

申请号：US12036476

申请日：2008-02-25

申请人： Kattamuri Ekanadham ,  Jennifer A. Navarro ,  Il Park ,  Chung-Lung Kevin Shum

发明人： Kattamuri Ekanadham ,  Jennifer A. Navarro ,  Il Park ,  Chung-Lung Kevin Shum

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/6026

摘要： A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system also includes a confidence counter. The system further includes eager prefetching control logic for performing a method when the stride size is less than a cache line size. The method includes adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern, comparing the confidence counter to a confidence threshold, and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold. The system may also include selection logic to select between the eager prefetching control logic and standard stride prefetching control logic.

摘要翻译： 提供了一种用于增强处理系统中的高速缓存存储器预取的及时性的系统，方法和计算机程序产品。 系统包括步幅图案检测器，用于检测作为连续高速缓存访​​问之间的差异的字节量的步幅大小的步幅图案。 系统还包括置信柜台。 该系统还包括用于当步幅大小小于高速缓存行大小时执行方法的迫切预取控制逻辑。 该方法包括响应于步幅模式检测器检测步幅模式来调整置信计数器，将置信计数器与置信阈值进行比较，以及响应于达到置信阈值的置信度计数器请求高速缓存预取。 系统还可以包括选择逻辑以在急切预取控制逻辑和标准步幅预取控制逻辑之间进行选择。

公开(公告)号：US20050091643A1

公开(公告)日：2005-04-28

申请号：US10695139

申请日：2003-10-28

申请人： Kattamuri Ekanadham ,  Pratap Pattnaik ,  Simone Sbaraglia ,  Luiz DeRose

发明人： Kattamuri Ekanadham ,  Pratap Pattnaik ,  Simone Sbaraglia ,  Luiz DeRose

IPC分类号： G06F3/00 ,  G06F9/44 ,  G06F11/34

CPC分类号： G06F11/3471 ,  G06F11/3476 ,  G06F2201/86

摘要： A method and apparatus for creating a compressed trace for a program, wherein events are compressed separately to provide improved compression and tracing. A sequence of events for a program is selected, and a sequence of values is then determined for each of the selected events occurring during an execution of the program. Each sequence of values is then compressed to generate a compressed sequence of values for each event. These values are then ordered in accordance with information stored in selected events (such as for example, branch events), where the ordered values correspond to the trace.

摘要翻译： 一种用于为程序创建压缩轨迹的方法和装置，其中分别压缩事件以提供改进的压缩和跟踪。 选择程序的事件序列，然后针对在执行程序期间发生的每个所选择的事件确定一系列值。 然后将每个值序列压缩以产生每个事件的压缩的值序列。 这些值然后根据存储在所选事件（例如分支事件）中的信息进行排序，其中有序值对应于跟踪。

公开(公告)号：US06321373B1

公开(公告)日：2001-11-20

申请号：US09431107

申请日：1999-10-30

申请人： Kattamuri Ekanadham ,  Jose Eduardo Moreira ,  Vijay Krishnarao Naik

发明人： Kattamuri Ekanadham ,  Jose Eduardo Moreira ,  Vijay Krishnarao Naik

IPC分类号： G06F944

CPC分类号： G06F9/5077

摘要： A system and method for dynamic scheduling and allocation of resources to parallel applications during the course of their execution. By establishing well-defined interactions between an executing job and the parallel system, the system and method support dynamic reconfiguration of processor partitions, dynamic distribution and redistribution of data, communication among cooperating applications, and various other monitoring actions. The interactions occur only at specific points in the execution of the program where the aforementioned operations can be performed efficiently.

摘要翻译： 一种在并行应用程序执行过程中动态调度和分配资源的系统和方法。 通过建立执行作业与并行系统之间的明确定义的交互，系统和方法支持处理器分区的动态重新配置，数据的动态分配和重新分配，协作应用之间的通信以及各种其他监控动作。 相互作用仅在执行上述操作有效执行的程序的特定点处发生。

公开(公告)号：US08683175B2

公开(公告)日：2014-03-25

申请号：US13048214

申请日：2011-03-15

申请人： Kattamuri Ekanadham ,  Hung Q. Le ,  Jose E. Moreira ,  Pratap C. Pattnaik

发明人： Kattamuri Ekanadham ,  Hung Q. Le ,  Jose E. Moreira ,  Pratap C. Pattnaik

IPC分类号： G06F9/30 ,  G06F12/10

CPC分类号： G06F9/3877 ,  G06F9/30043 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3851 ,  G06F12/1027

摘要： A method, system and computer program product are disclosed for interfacing between a multi-threaded processing core and an accelerator. In one embodiment, the method comprises copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core, and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads. Whenever any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for the any one of the threads. This facilitates starting that specified operation without memory translation faults. In an embodiment, the copying includes, each time one of the memory address translations is updated on the processing core, copying the updated one of the memory address translations to the hardware accelerator.

摘要翻译： 公开了用于在多线程处理核心和加速器之间进行接口的方法，系统和计算机程序产品。 在一个实施例中，该方法包括从处理核心复制到在处理核心上操作的多个线程中的每个线程的硬件加速器存储器地址转换，以及同时在硬件加速器上存储每个线程的一个或多个存储器地址转换 。 只要在处理核心上操作的多个线程中的任何一个指示硬件加速器执行指定的操作，则硬件加速器在其上存储有针对任何一个线程的一个或多个存储器地址转换。 这有助于启动指定的操作，而不会出现内存转换错误。 在一个实施例中，复制包括每次在处理核心上更新一个存储器地址转换时，将更新的一个存储器地址转换复制到硬件加速器。