公开(公告)号：US20070184597A1

公开(公告)日：2007-08-09

申请号：US11350160

申请日：2006-02-07

申请人： Igor Polishchuk ,  Krishnaswamy Ramkumar ,  Sagy Levy

发明人： Igor Polishchuk ,  Krishnaswamy Ramkumar ,  Sagy Levy

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

摘要： In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.

摘要翻译： 在一个实施例中，通过电介质层形成自对准接触（SAC）沟槽结构以暴露MOS晶体管的有源区。 SAC沟槽结构不仅暴露用于电连接的有源区，而且还去除了有源区上的应力衬垫的部分。 这使得应力衬垫主要在MOS晶体管的侧壁和顶部上方。 在有源区上去除应力衬垫的部分基本上消除了由衬底上的应力衬垫施加的应变的横向分量，从而允许改进的驱动电流而不会使互补MOS晶体管基本上降级。

公开(公告)号：US08860122B1

公开(公告)日：2014-10-14

申请号：US13114889

申请日：2011-05-24

申请人： Igor Polishchuk ,  Sagy Levy

发明人： Igor Polishchuk ,  Sagy Levy

IPC分类号： H01L29/792 ,  H01L27/115

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11563 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source and drain regions. A gate stack is above the substrate over the channel region and between the pair of source and drain regions. The gate stack includes a high dielectric constant blocking region.

摘要翻译： 描述了非易失性电荷陷阱存储器件。 该器件包括具有沟道区和一对源极和漏极区的衬底。 栅极堆叠在沟道区域上方的衬底之上以及在一对源极和漏极区域之间。 栅极堆叠包括高介电常数阻挡区域。

公开(公告)号：US08691648B1

公开(公告)日：2014-04-08

申请号：US13168711

申请日：2011-06-24

申请人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Soo Byun

发明人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Soo Byun

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： Non-volatile semiconductor memories and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method includes: (i) forming a gate for a non-volatile memory transistor on a surface of a substrate overlaying a channel region formed therein, the gate including a charge trapping layer; and (ii) forming a strain inducing structure over the gate of the non-volatile memory transistor to increase charge retention of the charge trapping layer. Preferably, the memory transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor comprising a SONOS gate stack. More preferably, the memory also includes a logic transistor on the substrate, and the step of forming a strain inducing structure comprises the step of forming the strain inducing structure over the logic transistor. Other embodiments are also disclosed.

摘要翻译： 提供非易失性半导体存储器及其制造方法以改善其性能。 在一个实施例中，该方法包括：（i）在覆盖其中形成的沟道区的衬底的表面上形成用于非易失性存储晶体管的栅极，栅极包括电荷俘获层; 和（ii）在非易失性存储晶体管的栅极上形成应变诱导结构，以增加电荷俘获层的电荷保留。 优选地，存储晶体管是包括SONOS栅极堆叠的氧化硅 - 氧化物 - 氮化物 - 氧化物 - 硅（SONOS）晶体管。 更优选地，存储器还包括在衬底上的逻辑晶体管，并且形成应变诱导结构的步骤包括在逻辑晶体管上形成应变诱导结构的步骤。 还公开了其他实施例。

公开(公告)号：US08592891B1

公开(公告)日：2013-11-26

申请号：US13539463

申请日：2012-07-01

申请人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Byun

发明人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Byun

IPC分类号： H01L29/76

CPC分类号： H01L29/4234 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor device and method of fabricating the same are provided. In one embodiment, the semiconductor device includes a memory transistor with an oxide-nitride-nitride-oxide (ONNO) stack disposed above a channel region. The ONNO stack comprises a tunnel dielectric layer disposed above the channel region, a multi-layer charge-trapping region disposed above the tunnel dielectric layer, and a blocking dielectric layer disposed above the multi-layer charge-trapping region. The multi-layer charge-trapping region includes a substantially trap-free layer comprising an oxygen-rich nitride and a trap-dense layer disposed above the trap-free layer. The semiconductor device further includes a strain inducing structure including a strain inducing layer disposed proximal to the ONNO stack to increase charge retention of the multi-layer charge-trapping region. Other embodiments are also disclosed.

摘要翻译： 提供了半导体器件及其制造方法。 在一个实施例中，半导体器件包括具有设置在沟道区上方的氧化氮化物 - 氮化物 - 氧化物（ONNO）堆的存储晶体管。 ONNO堆叠包括设置在沟道区上方的隧道介电层，设置在隧道介电层上方的多层电荷捕获区，以及设置在多层电荷俘获区上方的阻挡介质层。 多层电荷捕获区域包括基本上无陷阱层，其包含富含氧的氮化物和设置在无阱层之上的陷阱致密层。 半导体器件还包括应变诱导结构，其包括设置在ONNO堆叠附近的应变诱导层，以增加多层电荷俘获区域的电荷保留。 还公开了其他实施例。

公开(公告)号：US20130106796A1

公开(公告)日：2013-05-02

申请号：US13335522

申请日：2011-12-22

申请人： Esat Yilmaz ,  Vemund Kval Bakken ,  Igor Polishchuk ,  Kishore Sundara-Rajan

发明人： Esat Yilmaz ,  Vemund Kval Bakken ,  Igor Polishchuk ,  Kishore Sundara-Rajan

IPC分类号： G06F3/033

CPC分类号： G06F3/0383 ,  G06F3/03545

摘要： In one embodiment, a device includes a form factor of a stylus. The form factor includes a surface area. The device also includes one or more substrates disposed along one or more portions of the surface area; and one or more touch sensors disposed on one or more of the substrates. At least one of the touch sensors includes a distinct touch-sensitive area that includes a touch-sensitive button, a touch-sensitive wheel, or a touch-sensitive slider. The device also includes a computer-readable non-transitory storage medium coupled to one or more of the touch sensors and embodying logic configured to associate the distinct touch-sensitive area with a pre-determined function of the device.

摘要翻译： 在一个实施例中，设备包括触控笔的外形尺寸。 外形尺寸包括表面积。 该装置还包括沿表面区域的一个或多个部分设置的一个或多个基板; 以及设置在一个或多个基板上的一个或多个触摸传感器。 触摸传感器中的至少一个包括具有触敏按钮，触敏轮或触敏滑块的不同的触敏区域。 该设备还包括耦合到一个或多个触摸传感器的计算机可读的非暂时性存储介质，并且被配置为将不同的触敏区域与设备的预定功能相关联的体现逻辑。

公开(公告)号：US20130106731A1

公开(公告)日：2013-05-02

申请号：US13419087

申请日：2012-03-13

申请人： Esat Yilmaz ,  Trond Jarle Pedersen ,  John Logan ,  Vemund Kval Bakken ,  Kishore Sundara-Rajan ,  Joo Yong Um ,  Igor Polishchuk

发明人： Esat Yilmaz ,  Trond Jarle Pedersen ,  John Logan ,  Vemund Kval Bakken ,  Kishore Sundara-Rajan ,  Joo Yong Um ,  Igor Polishchuk

IPC分类号： G06F3/033

CPC分类号： G06F3/03545 ,  G06F3/017 ,  G06F3/0346 ,  G06F3/0416 ,  G06F3/044 ,  G06F3/046 ,  G06F3/04883 ,  G06F2203/0381 ,  G06F2203/0384 ,  G06F2203/04104 ,  G06F2203/04106 ,  G06F2203/04808

摘要： In one embodiment, a stylus with one or more electrodes and one or more computer-readable non-transitory storage media embodying logic for transmitting signals wirelessly to a device through a touch sensor of the device has one or more sensors for detecting movement of the stylus.

摘要翻译： 在一个实施例中，具有一个或多个电极的触针和一个或多个计算机可读非瞬态存储介质，其包含用于通过设备的触摸传感器无线地将信号传输到设备的逻辑，具有用于检测触控笔的移动的一个或多个传感器 。

公开(公告)号：US07629653B1

公开(公告)日：2009-12-08

申请号：US11827765

申请日：2007-07-13

申请人： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

发明人： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

IPC分类号： H01L29/78

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

摘要翻译： 在一个实施例中，集成电路包括具有包括P +掺杂栅极多晶硅层和氮化栅极氧化物（NGOX）层的栅极堆叠的PMOS晶体管。 NGOX层可以在硅衬底之上。 集成电路还包括形成在晶体管上的互连线。 互连线包括吸氢材料，并且可以包括单一材料或材料堆。 互连线有利地吸收否则将被捕获在NGOX层/硅衬底界面中的氢（例如，H 2或H 2 O），从而改善晶体管的负偏压温度不稳定性（NBTI）寿命。

公开(公告)号：US09354728B2

公开(公告)日：2016-05-31

申请号：US13335522

申请日：2011-12-22

申请人： Esat Yilmaz ,  Vemund Kval Bakken ,  Igor Polishchuk ,  Kishore Sundara-Rajan

发明人： Esat Yilmaz ,  Vemund Kval Bakken ,  Igor Polishchuk ,  Kishore Sundara-Rajan

IPC分类号： G06F3/038 ,  G06F3/0354

CPC分类号： G06F3/0383 ,  G06F3/03545

摘要： In one embodiment, a device includes a form factor of a stylus. The form factor includes a surface area. The device also includes one or more substrates disposed along one or more portions of the surface area; and one or more touch sensors disposed on one or more of the substrates. At least one of the touch sensors includes a distinct touch-sensitive area that includes a touch-sensitive button, a touch-sensitive wheel, or a touch-sensitive slider. The device also includes a computer-readable non-transitory storage medium coupled to one or more of the touch sensors and embodying logic configured to associate the distinct touch-sensitive area with a pre-determined function of the device.

摘要翻译： 在一个实施例中，设备包括触控笔的外形尺寸。 外形尺寸包括表面积。 该装置还包括沿表面区域的一个或多个部分设置的一个或多个基板; 以及设置在一个或多个基板上的一个或多个触摸传感器。 触摸传感器中的至少一个包括具有触敏按钮，触敏轮或触敏滑块的不同的触敏区域。 该设备还包括耦合到一个或多个触摸传感器的计算机可读的非暂时性存储介质，并且被配置为将不同的触敏区域与设备的预定功能相关联的体现逻辑。

公开(公告)号：US08174510B2

公开(公告)日：2012-05-08

申请号：US12413580

申请日：2009-03-29

申请人： Igor Polishchuk ,  Edward Grivna

发明人： Igor Polishchuk ,  Edward Grivna

IPC分类号： G06F3/045

CPC分类号： G06F3/044 ,  G06F2203/04112

摘要： One embodiment in accordance with the invention can include a capacitive touch screen. The capacitive touch screen includes a substantially transparent substrate and a plurality of electrodes formed on the substantially transparent substrate. The plurality of electrodes are substantially parallel in a first direction and each of the plurality of electrodes includes a layer of light altering material.

摘要翻译： 根据本发明的一个实施例可以包括电容式触摸屏。 电容式触摸屏包括基本上透明的基板和形成在基本上透明的基板上的多个电极。 多个电极在第一方向上基本平行，并且多个电极中的每一个包括一层光改变材料。

公开(公告)号：US06794234B2

公开(公告)日：2004-09-21

申请号：US10315476

申请日：2002-12-09

申请人： Igor Polishchuk ,  Pushkar Ranade ,  Tsu-Jae King ,  Chenming Hu

发明人： Igor Polishchuk ,  Pushkar Ranade ,  Tsu-Jae King ,  Chenming Hu

IPC分类号： H01L218238

CPC分类号： H01L21/28079 ,  H01L21/823842 ,  H01L29/4958

摘要： A gate structure for a MOSFET device comprises a gate insulation layer, a first layer of a first metal abutting the gate insulation layer, and a second layer overlying the first layer and comprising a mixture of the metal of the first layer and a second metal, the metal layers formed by the diffusion of the first metal into and through the second metal. The second metal can be used as the gate for a n-MOS transistor, and the mixture of first metal and second metal overlying a layer of the first metal can be used as a gate for a p-MOS transistor where the first metal has a work function of about 5.2 eV and the second metal has a work function of about 4.1 eV.