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    Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors
    1.
    发明授权
    Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors 有权
    改善场效应晶体管负偏压温度不稳定性（NBTI）寿命的技术

    公开(公告)号：US07256087B1

    公开(公告)日：2007-08-14

    申请号：US11018422

    申请日：2004-12-21

    申请人： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

    发明人： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823842

    摘要： In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

    摘要翻译： 在一个实施例中，集成电路包括具有包括P +掺杂栅极多晶硅层和氮化栅极氧化物（NGOX）层的栅极堆叠的PMOS晶体管。 NGOX层可以在硅衬底之上。 集成电路还包括形成在晶体管上的互连线。 互连线包括吸氢材料，并且可以包括单一材料或材料堆。 互连线有利地吸收否则将被捕获在NGOX层/硅衬底界面中的氢（例如，H 2 H 2或H 2 O 2），从而提高负偏压温度 晶体管的不稳定性（NBTI）寿命。

    Integration of non-volatile charge trap memory devices and logic CMOS devices
    2.
    发明授权
    Integration of non-volatile charge trap memory devices and logic CMOS devices 有权
    集成非易失性电荷陷阱存储器件和逻辑CMOS器件

    公开(公告)号：US08143129B2

    公开(公告)日：2012-03-27

    申请号：US12185747

    申请日：2008-08-04

    申请人： Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Jeremy Warren

    发明人： Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Jeremy Warren

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

    摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

    摘要翻译： 一种半导体结构及其形成方法。 半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。 可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。 可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。 在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。 可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

    Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors
    3.
    发明授权
    Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors 有权
    改善场效应晶体管负偏压温度不稳定性（NBTI）寿命的技术

    公开(公告)号：US07629653B1

    公开(公告)日：2009-12-08

    申请号：US11827765

    申请日：2007-07-13

    申请人： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

    发明人： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823857 ,  H01L21/823842

    摘要： In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

    摘要翻译： 在一个实施例中，集成电路包括具有包括P +掺杂栅极多晶硅层和氮化栅极氧化物（NGOX）层的栅极堆叠的PMOS晶体管。 NGOX层可以在硅衬底之上。 集成电路还包括形成在晶体管上的互连线。 互连线包括吸氢材料，并且可以包括单一材料或材料堆。 互连线有利地吸收否则将被捕获在NGOX层/硅衬底界面中的氢（例如，H 2或H 2 O），从而改善晶体管的负偏压温度不稳定性（NBTI）寿命。

    Memory cell array latchup prevention
    8.
    发明申请
    Memory cell array latchup prevention 有权
    存储单元阵列闭锁预防

    公开(公告)号：US20050286295A1

    公开(公告)日：2005-12-29

    申请号：US10877313

    申请日：2004-06-25

    申请人： Ravindra Kapre ,  Shahin Sharifzadeh

    发明人： Ravindra Kapre ,  Shahin Sharifzadeh

    IPC分类号： G11C5/14 ,  G11C11/34 ,  H01L27/092 ,  H02H9/02

    CPC分类号： G11C11/417 ,  G11C5/14 ,  H01L27/0921 ,  H02H9/025

    摘要： A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit. The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.

    摘要翻译： 提供了一种互补场效应（CMOS）电路，其包括沿该电路的电源总线或接地总线布置的限流装置。 限流器件被配置为防止CMOS电路的锁存。 更具体地，限流装置被配置为保持寄生pnpn二极管结构的结为反向偏置。 还提供了一种方法，其包括产生布置在第一CMOS电路内的pnpn二极管的电压 - 电压曲线图，该第一CMOS电路不存在沿着该电路的电力总线布置的限流装置。 此外，该方法包括从电流 - 电压图确定保持电流电平，并且限制限流器件沿着包括与第一CMOS电路相似的设计规范的第二CMOS电路的电源总线放置，使得通过 第二CMOS电路不超过保持电流电平。