公开(公告)号：US20050177831A1

公开(公告)日：2005-08-11

申请号：US10775448

申请日：2004-02-10

Applicant: James Goodman ,  Ravi Rajwar

Inventor： James Goodman ,  Ravi Rajwar

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3842 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/528

Abstract: Hardware resolution of data conflicts in critical sections of programs executed in shared memory computer architectures are resolved using a hardware-based ordering system and without acquisition of the lock variable.

Abstract translation: 在共享存储器计算机体系结构中执行的程序的关键部分中数据冲突的硬件解决方案使用基于硬件的订购系统进行解决，而无需获取锁定变量。

公开(公告)号：US07009419B2

公开(公告)日：2006-03-07

申请号：US10687165

申请日：2003-10-16

Applicant: James Goodman

Inventor： James Goodman

IPC: H03K19/00 ,  H04L9/00

CPC classification number: G06F21/74 ,  G01R31/31704 ,  G01R31/31719 ,  G01R31/318558 ,  G01R31/318588

Abstract: A method and circuit for preventing external access to secure data of an integrated circuit while supporting DFT is disclosed. In accordance with the method the integrated circuit is automatically placed into the test mode at integrated circuit power-up from a power-down state. At power up, secure data is other than present within a secure data-path of the integrated circuit. Access is provided to the secure data path via a second data path coupled with the first secure data-path. Via the access path, data other than secure data is provided to the integrated circuit, the data for performing test functions of the integrated circuit operating in the test mode. Once data other than secure data is provided to first secure data path, the test mode is terminated and access via other than the secure ports is disabled. The test mode is only re-entered by powering down the integrated circuit and re-initialising it.

公开(公告)号：US20050091944A1

公开(公告)日：2005-05-05

申请号：US10976608

申请日：2004-10-29

Applicant: James Goodman

Inventor： James Goodman

IPC: B31B50/48 ,  B65B7/20

CPC classification number: B65B7/20

Abstract: A flaps closing apparatus for closing full flap boxes is provided. The apparatus includes a flaps closing assembly with a first brake mechanism and closing bars with a second brake mechanism. The first brake mechanism controls the vertical motion of the flaps closing assembly with respect to the flaps closing apparatus. The second brake mechanism holds the closing bars in an angled configuration and at a first predetermined vertical position permits the bars to pivot to a horizontal configuration. A flap sealing assembly includes a pair of compression plates positioned outside the flaps closing assembly. A compression plate actuating mechanism draws the compression plates inwardly to urge side flaps of the full flap box into contact with sides of the full flap box at a second predetermined vertical position. A vertical movement mechanism lowers and raises the apparatus.

Abstract translation: 提供一种用于关闭整个皮瓣盒的折片关闭装置。 该装置包括具有第一制动机构的挡板关闭组件和具有第二制动机构的关闭杆。 第一制动机构控制翼片关闭组件相对于翼片关闭装置的垂直运动。 第二制动机构将闭合杆保持成倾斜的构造，并且在第一预定垂直位置允许杆枢转到水平构型。 翼片密封组件包括位于翼片关闭组件外侧的一对压板。 压缩板致动机构向内拉动压板以促使完整挡板的侧翼在第二预定垂直位置处与完全挡板的侧面接触。 垂直移动机构降低并升高装置。

公开(公告)号：US06466048B1

公开(公告)日：2002-10-15

申请号：US09862339

申请日：2001-05-23

Applicant: James Goodman

Inventor： James Goodman

IPC: H03K1900

CPC classification number: G06F21/74 ,  G01R31/31704 ,  G01R31/31719 ,  G01R31/318558 ,  G01R31/318588

Abstract: A method and circuit for preventing external access to secure data of an integrated circuit while supporting DFT is disclosed. In accordance with the method the integrated circuit is automatically placed into the test mode at integrated circuit power-up from a power-down state. At power up, secure data is other than present within a secure data-path of the integrated circuit. Access is provided to the secure data path via a second data path coupled with the first secure data-path. Via the access path, data other than secure data is provided to the integrated circuit, the data for performing test functions of the integrated circuit operating in the test mode. Once data other than secure data is provided to first secure data path, the test mode is terminated and access via other than the secure ports is disabled. The test mode is only re-entered by powering down the integrated circuit and re-initializing it.

Abstract translation: 公开了一种用于在支持DFT的同时防止外部访问集成电路的安全数据的方法和电路。 根据该方法，集成电路在从掉电状态的集成电路上电时自动进入测试模式。 在上电时，安全数据不同于存在于集成电路的安全数据路径内。 经由与第一安全数据路径耦合的第二数据路径向安全数据路径提供访问。 通过访问路径，除了安全数据之外的数据被提供给集成电路，用于执行在测试模式下操作的集成电路的测试功能的数据。 一旦将安全数据以外的数据提供给第一安全数据路径，则终止测试模式，并且禁用除安全端口之外的访问。 测试模式只能通过关闭集成电路并重新初始化来重新输入。