公开(公告)号：US20070217108A1

公开(公告)日：2007-09-20

申请号：US11516611

申请日：2006-09-07

申请人： Hidekiyo Ozawa ,  Morihito Hasegawa

发明人： Hidekiyo Ozawa ,  Morihito Hasegawa

IPC分类号： H02H3/08

CPC分类号： H02M3/158 ,  H02M2001/008 ,  H02M2001/009 ,  Y10T307/469

摘要： It is intended to provide a control circuit of power supply, a power supply and a control method thereof capable of achieving power saving in an integrated circuit and reducing a delay time of the integrated circuit. The control circuit 50 of a power supply 10 which outputs plural DC voltages VCC, VBGP, VBGN each having a different voltage value includes a voltage changing portion SW1 which detects an output current I1 relating to a first DC voltage VCC which is one of the plural DC voltages and sets at least one DC voltage except the first DC voltage VCC based on the detected output current I1, and the like.

摘要翻译： 旨在提供能够实现集成电路中的省电并且减少集成电路的延迟时间的电源的控制电路，电源及其控制方法。 输出各具有不同电压值的多个直流电压VCC，VBGP，VBGN的电源10的控制电路50包括：电压变化部SW 1，其检测与作为以下之一的第一直流电压VCC相关的输出电流I 1 多个DC电压并且基于检测到的输出电流I 1设置除了第一DC电压VCC之外的至少一个DC电压等。

公开(公告)号：US07948219B2

公开(公告)日：2011-05-24

申请号：US11902706

申请日：2007-09-25

申请人： Morihito Hasegawa ,  Hidekiyo Ozawa

发明人： Morihito Hasegawa ,  Hidekiyo Ozawa

IPC分类号： G05F1/618

CPC分类号： H02M3/1588 ,  Y02B70/1466

摘要： The control circuit comprises: a detecting portion COMP1 for detecting a status transition of a first signal FR at the connecting point P which changes at a constant cycle corresponding to current flowing through the antiparallel diode D when the main switch device FET is turned OFF; and a phase difference adjusting portion 30, 40 for adjusting the phase difference by adjusting the output timing of the second signal FP corresponding to a phase difference between the phase of the first signal FR detected by the detecting portion COMP1 and the phase of the second signal FP generated based on the first signal of one cycle before and the rectification switch device FET2 is turned ON corresponding to the second signal FP whose output timing is adjusted by the phase difference adjusting portion 30, 40.

摘要翻译： 控制电路包括：检测部分COMP1，用于检测连接点P处的第一信号FR的状态转变，当主开关器件FET截止时，连接点P以与流过反并联二极管D的电流相对应的恒定周期变化; 以及相位差调整部分30,40，用于通过调节与由检测部分COMP1检测的第一信号FR的相位与第二信号的相位之间的相位差相对应的第二信号FP的输出定时来调整相位差 基于前一周期的第一信号产生的FP和整流开关器件FET2导通，相应于由相位差调节部分30,40调节输出定时的第二信号FP。

公开(公告)号：US20080079408A1

公开(公告)日：2008-04-03

申请号：US11902706

申请日：2007-09-25

申请人： Morihito Hasegawa ,  Hidekiyo Ozawa

发明人： Morihito Hasegawa ,  Hidekiyo Ozawa

IPC分类号： G05F1/44 ,  G05F1/00

CPC分类号： H02M3/1588 ,  Y02B70/1466

摘要： The control circuit comprises: a detecting portion COMP1 for detecting a status transition of a first signal FR at the connecting point P which changes at a constant cycle corresponding to current flowing through the antiparallel diode D when the main switch device FET is turned OFF; and a phase difference adjusting portion 30, 40 for adjusting the phase difference by adjusting the output timing of the second signal FP corresponding to a phase difference between the phase of the first signal FR detected by the detecting portion COMP1 and the phase of the second signal FP generated based on the first signal of one cycle before and the rectification switch device FET2 is turned ON corresponding to the second signal FP whose output timing is adjusted by the phase difference adjusting portion 30, 40.

摘要翻译： 该控制电路包括：检测部分COMP1，用于检测在主开关器件FET截止时，在连接点P处的第一信号FR的状态转变，其以与流过反并联二极管D的电流相对应的恒定周期变化; 以及相位差调整部分30,40，用于通过调节与由检测部分COMP 1检测的第一信号FR的相位与第二信号FP的相位之间的相位差相对应的第二信号FP的输出定时来调节相位差 基于前一周期的第一信号产生的信号FP和整流开关器件FET2导通，相应于由相位差调节部分30,40调节输出定时的第二信号FP。

公开(公告)号：US07298117B2

公开(公告)日：2007-11-20

申请号：US11362513

申请日：2006-02-27

申请人： Morihito Hasegawa ,  Hidekiyo Ozawa ,  Shoji Tajiri ,  Toshihiko Kasai

发明人： Morihito Hasegawa ,  Hidekiyo Ozawa ,  Shoji Tajiri ,  Toshihiko Kasai

IPC分类号： G05F1/10

CPC分类号： H02M1/36 ,  H02M3/156 ,  H02M2003/078 ,  H03K17/302 ,  H03K2217/0018

摘要： The invention provides a DC-DC converter capable of being started up in a state in which an input voltage is low and capable of being structured without increasing a circuit size. A back-gate voltage (Vsb) is outputted from a back-gate voltage generating circuit (VBGN), and is inputted to a back gate of a transistor (FET1). During a period during which an output voltage (Vout) is lower than a reference voltage (e0), an oscillation signal (OS1) is inputted to a gate of the transistor (FET1), and the back-gate voltage (Vsb) is set at a grounded voltage. Therefore, the transistor (FET1) has a reference threshold voltage (Vto). On the other hand, during a period during which the output voltage (Vout) is higher than the reference voltage (e0), a pulse signal (PS) is inputted to the gate of the transistor (FET1), and the back-gate voltage (Vsb) is set at an output voltage of a charge pump portion (5). Therefore, the transistor (FET1) has a threshold voltage higher than the reference threshold voltage (Vto).

摘要翻译： 本发明提供一种DC-DC转换器，其能够在输入电压低的状态下启动并且能够在不增加电路尺寸的情况下被构造。 背栅电压（Vsb）从背栅极电压产生电路（VBGN）输出，并被输入到晶体管（FET1）的背栅极。 在输出电压（Vout）低于基准电压（e 0）的期间，将振荡信号（OS1）输入到晶体管（FET1）的栅极，将栅极电压（Vsb ）设置在接地电压。 因此，晶体管（FET1）具有参考阈值电压（Vto）。 另一方面，在输出电压（Vout）高于基准电压（e 0）的期间，将脉冲信号（PS）输入到晶体管（FET1）的栅极， 栅极电压（Vsb）设定在电荷泵部（5）的输出电压。 因此，晶体管（FET1）具有高于参考阈值电压（Vto）的阈值电压。

公开(公告)号：US20070052398A1

公开(公告)日：2007-03-08

申请号：US11350720

申请日：2006-02-10

申请人： Morihito Hasegawa ,  Hidekiyo Ozawa

发明人： Morihito Hasegawa ,  Hidekiyo Ozawa

IPC分类号： G05F1/00

CPC分类号： H02M3/1588 ,  H02M3/1584 ,  Y02B70/1466

摘要： A differential output DC-DC converter capable of decreasing power consumption is presented. The differential output DC-DC converter 1 comprises output terminals VP and VM connected to both ends of load, and a switching regulator 10 for passing a source current. It further comprises a third transistor FET3, a choke coil L2, and a fourth transistor FET4 for rectifying a sink current in a flowing direction, and further a second regulator for allowing the sink current to flow, and issuing a voltage higher than a grounding point GND voltage and lower than a voltage of an output terminal VP, to an output terminal VM.

摘要翻译： 提出了能够降低功耗的差分输出DC-DC转换器。 差分输出DC-DC转换器1包括连接到负载两端的输出端子VP和VM以及用于使源电流通过的开关调节器10。 它还包括用于整流流动方向的吸收电流的第三晶体管FET 3，扼流线圈L 2和第四晶体管FET 4，以及用于允许吸收电流流动的第二调节器，并且发出高于 接地点GND电压并低于输出端子VP的电压输出到输出端子VM。

公开(公告)号：US07705483B2

公开(公告)日：2010-04-27

申请号：US11526051

申请日：2006-09-25

申请人： Hidekiyo Ozawa ,  Morihito Hasegawa

发明人： Hidekiyo Ozawa ,  Morihito Hasegawa

IPC分类号： H02J3/00 ,  H02J1/00 ,  H02J1/04

CPC分类号： H02M3/156 ,  H02M2001/008 ,  H02M2001/009 ,  Y10T307/281 ,  Y10T307/406

摘要： An object of the present invention is to provide a DC-DC converter control circuit capable of maintaining, even when any one of a plural number of DC-DC converters enters the abnormal state due to the occurrence of a failure, a voltage relationship between the output voltage of the faulty DC-DC converter and the output voltage of another DC-DC converter. An error amplifier ERA1G has an inverting input, a first non-inverting input, and a second non-inverting input. A first divided voltage VV1 provided from a first voltage divider circuit VD1 is fed into the inverting input; a reference voltage e1G from ground is fed into the first non-inverting input; and a second divided voltage VV2 provided from a second voltage divider circuit VD2 is fed into the second non-inverting input. The error amplifier ERA1G amplifies the error between the lower of the two voltage inputs fed into the two non-inverting inputs (i.e. the lower of the reference voltage e1G and the second divided voltage VV2), and the first divided voltage VV1 fed into the inverting input. The output terminal of the error amplifier ERA1G is connected to the input terminal of a PWM unit P1G.

摘要翻译： 本发明的一个目的是提供一种DC-DC转换器控制电路，即使当多个DC-DC转换器中的任何一个由于发生故障而进入异常状态时，也能够维持 故障DC-DC转换器的输出电压和另一个DC-DC转换器的输出电压。 误差放大器ERA1G具有反相输入，第一同相输入和第二同相输入。 从第一分压电路VD1提供的第一分压VV1被馈送到反相输入端; 来自地的参考电压e1G被馈送到第一同相输入端; 并且从第二分压器电路VD2提供的第二分压VV2被馈送到第二同相输入端。 误差放大器ERA1G放大馈送到两个同相输入端的两个电压输入的较低端（即，参考电压e1G和第二分压VV2的较低者）之间的误差，并将第一分压VV1馈入反相 输入。 误差放大器ERA1G的输出端连接到PWM单元P1G的输入端。

公开(公告)号：US20080197821A1

公开(公告)日：2008-08-21

申请号：US12032016

申请日：2008-02-15

申请人： Morihito Hasegawa ,  Hidekiyo Ozawa

发明人： Morihito Hasegawa ,  Hidekiyo Ozawa

IPC分类号： G05F1/00

CPC分类号： H02M1/36 ,  H02M1/32 ,  H02M3/156 ,  Y10S323/901

摘要： A DC-DC conversion circuit is configured by including a plurality of control signal generation circuits, a plurality of soft-start control circuits, and a start control circuit. The plurality of control signal generation circuits correspond to the plurality of control signals, and generate a corresponding control signal of the plurality of control signals based on a corresponding output value of a plurality of output values. The plurality of soft-start control circuits correspond to the plurality of control signals, and control a variation of the corresponding control signal at a start time of the DC-DC conversion circuit. The start control circuit instructs the corresponding soft-start control circuit to start operation in accordance with a change of the control signal taking part in an output control at the start time of the DC-DC conversion circuit.

摘要翻译： DC-DC转换电路通过包括多个控制信号生成电路，多个软启动控制电路和起动控制电路构成。 多个控制信号生成电路对应于多个控制信号，并且基于多个输出值的相应输出值生成多个控制信号的对应控制信号。 多个软启动控制电路对应于多个控制信号，并且在DC-DC转换电路的开始时间控制对应的控制信号的变化。 启动控制电路指示相应的软启动控制电路根据在DC-DC转换电路的开始时间中参与输出控制的控制信号的变化而开始工作。

公开(公告)号：US20070210649A1

公开(公告)日：2007-09-13

申请号：US11526051

申请日：2006-09-25

申请人： Hidekiyo Ozawa ,  Morihito Hasegawa

发明人： Hidekiyo Ozawa ,  Morihito Hasegawa

IPC分类号： H02J1/00

CPC分类号： H02M3/156 ,  H02M2001/008 ,  H02M2001/009 ,  Y10T307/281 ,  Y10T307/406

摘要： An object of the present invention is to provide a DC-DC converter control circuit capable of maintaining, even when any one of a plural number of DC-DC converters enters the abnormal state due to the occurrence of a failure, a voltage relationship between the output voltage of the faulty DC-DC converter and the output voltage of another DC-DC converter. An error amplifier ERA1G has an inverting input, a first non-inverting input, and a second non-inverting input. A first divided voltage VV1 provided from a first voltage divider circuit VD1 is fed into the inverting input; a reference voltage e1G from ground is fed into the first non-inverting input; and a second divided voltage VV2 provided from a second voltage divider circuit VD2 is fed into the second non-inverting input. The error amplifier ERA1G amplifies the error between the lower of the two voltage inputs fed into the two non-inverting inputs (i.e. the lower of the reference voltage e1G and the second divided voltage VV2), and the first divided voltage VV1 fed into the inverting input. The output terminal of the error amplifier ERA1G is connected to the input terminal of a PWM unit P1G.

摘要翻译： 本发明的一个目的是提供一种DC-DC转换器控制电路，即使当多个DC-DC转换器中的任何一个由于发生故障而进入异常状态时，也能够维持 故障DC-DC转换器的输出电压和另一个DC-DC转换器的输出电压。 误差放大器ERA1G具有反相输入，第一同相输入和第二同相输入。 从第一分压器电路VD1提供的第一分压VV1馈送到反相输入端; 来自地的参考电压e 1 G被馈送到第一同相输入端; 并且从第二分压器电路VD 2​​提供的第二分压VV 2被馈送到第二同相输入端。 误差放大器ERA 1 G放大馈入两个非反相输入端的两个电压输入的较低端之间的误差（即，参考电压e 1 G和第二分压VV 2的较低者），第一分压 VV 1馈入反相输入。 误差放大器ERA1G的输出端连接到PWM单元P 1 G的输入端。

公开(公告)号：US20070194766A1

公开(公告)日：2007-08-23

申请号：US11447009

申请日：2006-06-06

申请人： Hidekiyo Ozawa ,  Morihito Hasegawa ,  Toru Nakamura

发明人： Hidekiyo Ozawa ,  Morihito Hasegawa ,  Toru Nakamura

IPC分类号： G05F1/577

CPC分类号： H02M3/156 ,  H02M3/33561 ,  H02M2001/008 ,  Y10T307/414

摘要： An object of the present invention is to provide a DC-DC converter control circuit that, even when a plurality of output voltages of DC-DC converters is controlled independently of one another, can maintain a predetermined relationship of voltages established among the output voltages. A first reference voltage with which a high-potential back-gate voltage is controlled and a second reference voltage with which a supply voltage is controlled are dynamically controlled to be varied independently from one another. A supply voltage is applied to the inverting input terminal of a second differential-input amplifier. The second reference voltage is applied to the first non-inverting input terminal of the second differential-input amplifier, and the first reference voltage for a first DC-DC converter is applied to the second non-inverting input terminal thereof. The second differential-input amplifier amplifies the difference between a lower one of the first and second reference voltages applied to the two non-inverting input terminals thereof and the supply voltage applied to the inverting input terminal thereof.

摘要翻译： 本发明的目的是提供一种DC-DC转换器控制电路，即使在DC-DC转换器的多个输出电压彼此独立地被控制的情况下，也可以保持在输出电压之间建立的电压的预定关系。 控制高电位背栅极电压的第一参考电压和控制电源电压的第二参考电压被动态地控制以彼此独立地变化。 电源电压被施加到第二差分输入放大器的反相输入端子。 第二参考电压被施加到第二差分输入放大器的第一非反相输入端，并且第一DC-DC转换器的第一参考电压被施加到第二非反相输入端。 第二差分输入放大器放大施加到其两个非反相输入端的第一和第二参考电压中的较低的一个和施加到其反相输入端的电源电压之间的差。

公开(公告)号：US20060164050A1

公开(公告)日：2006-07-27

申请号：US11121084

申请日：2005-05-04

申请人： Morihito Hasegawa ,  Hidekiyo Ozawa

发明人： Morihito Hasegawa ,  Hidekiyo Ozawa

IPC分类号： G05F1/618 ,  G05F1/56

CPC分类号： H02M3/1584

摘要： A self-excited multi-phase DC-DC converter having satisfactory responsiveness when its load suddenly changes. A control unit of the converter compares output currents of first and second converter units. Based on the comparison result, the control unit generates control signals to operate a converter unit through which a smaller output current flows. For example, when an output voltage of the converter decreases due to a sudden change in the load while the first converter unit is operating to supply current, the second converter unit through which a smaller output current flows is operated to increase the output voltage.

摘要翻译： 一种自激式多相DC-DC转换器，当其负载突然变化时具有令人满意的响应能力。 转换器的控制单元比较第一和第二转换器单元的输出电流。 基于比较结果，控制单元产生控制信号以操作较小输出电流流过的转换器单元。 例如，当第一转换器单元正在运行以提供电流时，由于负载突然变化而导致转换器的输出电压下降，所以操作较小输出电流流动的第二转换器单元被增加输出电压。