Memory including a 1R1RW bitcell storage array and methods thereof

    公开(公告)号:US11276458B2

    公开(公告)日:2022-03-15

    申请号:US17080242

    申请日:2020-10-26

    Abstract: A memory and a signal processing method are provided. The memory includes a latch circuit, a decoding circuit, a storage array, a read circuit, and a write circuit. The storage array includes M rows and N columns of bitcells. The latch circuit is configured to receive a first address and a second address. The decoding circuit is configured to: determine a first bitcell based on the first address, and determine a second bitcell based on the second address. The write circuit is configured to: receive data, and write the data into the first bitcell through a first port of the first bitcell. The read circuit is configured to read, through the first port of the first bitcell, data stored in the first bitcell; and is further configured to read, through a second port of the second bitcell, data stored in the second bitcell. Implementing this application can implement 1R1RW.

    Electrostatic Discharge Protection Apparatus and Integrated Circuit with Multiple Power Domains

    公开(公告)号:US20180062387A1

    公开(公告)日:2018-03-01

    申请号:US15687252

    申请日:2017-08-25

    Inventor: Mei Li Bingwu Ji Yu Xia

    CPC classification number: H02H9/046 H01L27/0255 H01L27/0266 H01L27/0292

    Abstract: This application discloses an electrostatic discharge protection apparatus and an integrated circuit with multiple power domains. The electrostatic discharge protection apparatus includes a diode and an NMOS transistor. A positive electrode of the diode is coupled to a first interface, a negative electrode of the diode is coupled to a first electrode of the NMOS transistor, both a second electrode of the NMOS transistor and a gate electrode of the NMOS transistor are coupled to a second interface, and a substrate of the NMOS transistor is used for grounding. At least one electrostatic discharge protection apparatus may be disposed in the integrated circuit with multiple power domains.

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