公开(公告)号：US12068202B2

公开(公告)日：2024-08-20

申请号：US17244410

申请日：2021-04-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sunhom Steve Paak ,  Xiaolong Ma ,  Yanxiang Liu ,  Daxiang Wang ,  Zanfeng Chen ,  Yu Xia ,  Huabin Chen ,  Yongjie Zhou

IPC: H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823481 ,  H01L21/0259 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: This application provides an integrated circuit device and a preparation method thereof, and relates to the field of semiconductor technologies. An isolation section for suppressing a leakage current path of two adjacent transistors may be formed by using a simple process. The integrated circuit device includes a substrate and a fin protruding from the substrate. The integrated circuit device further includes two adjacent transistors. The two adjacent transistors use two spaced segments on the fin as respective channels of the two adjacent transistors. A part that is of the fin and that is located between the two spaced segments is processed to obtain an isolation section. The isolation section is used to suppress current transfer between the two channels of the two adjacent transistors.

公开(公告)号：US20190181108A1

公开(公告)日：2019-06-13

申请号：US16279435

申请日：2019-02-19

Applicant: Huawei Technologies Co., Ltd.

Inventor： Cheng Ting Chen ,  Sheng Chieh Chang ,  Yu Xia

IPC: H01L23/00

Abstract: A semiconductor package structure includes a connection pad disposed on a semiconductor component. A protective layer includes a first non-conductive material, a first part, and a second part. The first part covers the semiconductor component except the connection pad, a surface of the first part is at a first height, the second part covers a periphery of the connection pad, a surface of the second part is at a second height, the first height is less than the second height, a middle part of the connection pad is exposed, and the first part and the second part are connected at an edge of the connection pad.

公开(公告)号：US20210249311A1

公开(公告)日：2021-08-12

申请号：US17244410

申请日：2021-04-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sunhom Steve Paak ,  Xiaolong Ma ,  Yanxiang Liu ,  Daxiang Wang ,  Zanfeng Chen ,  Yu Xia ,  Huabin Chen ,  Yongjie Zhou

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: This application provides an integrated circuit device and a preparation method thereof, and relates to the field of semiconductor technologies. An isolation section for suppressing a leakage current path of two adjacent transistors may be formed by using a simple process. The integrated circuit device includes a substrate and a fin protruding from the substrate. The integrated circuit device further includes two adjacent transistors. The two adjacent transistors use two spaced segments on the fin as respective channels of the two adjacent transistors. Apart that is of the fin and that is located between the two spaced segments is processed to obtain an isolation section. The isolation section is used to suppress current transfer between the two channels of the two adjacent transistors.

公开(公告)号：US10784679B2

公开(公告)日：2020-09-22

申请号：US15687252

申请日：2017-08-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Mei Li ,  Bingwu Ji ,  Yu Xia

IPC: H02H9/04 ,  H01L27/02

Abstract: This application discloses an electrostatic discharge protection apparatus and an integrated circuit with multiple power domains. The electrostatic discharge protection apparatus includes a diode and an NMOS transistor. A positive electrode of the diode is coupled to a first interface, a negative electrode of the diode is coupled to a first electrode of the NMOS transistor, both a second electrode of the NMOS transistor and a gate electrode of the NMOS transistor are coupled to a second interface, and a substrate of the NMOS transistor is used for grounding. At least one electrostatic discharge protection apparatus may be disposed in the integrated circuit with multiple power domains.

公开(公告)号：US10164613B2

公开(公告)日：2018-12-25

申请号：US15676788

申请日：2017-08-14

Applicant: Huawei Technologies Co., Ltd.

Inventor： Qi Chen ,  Jianfu Zhong ,  Qiuling Zeng ,  Yu Xia

IPC: H03K3/012 ,  H03K5/159

Abstract: A phase-inverted clock generation circuit is provided, where sources of a first PMOS and a second PMOS are connected to a power source, drains of the first PMOS and the second PMOS are connected to a source of a third PMOS, and a drain of the third PMOS is connected to a drain of a third NMOS; and the drain of the third PMOS is connected to a drain of a second NMOS, a source of the second NMOS is connected to a drain of a first NMOS, and a source of the first NMOS and a source of the third NMOS.

公开(公告)号：US20180048297A1

公开(公告)日：2018-02-15

申请号：US15676788

申请日：2017-08-14

Applicant: Huawei Technologies Co., Ltd.

Inventor： Qi Chen ,  Jianfu Zhong ,  Qiuling Zeng ,  Yu Xia

IPC: H03K3/012 ,  H03K5/159

CPC classification number: H03K3/012 ,  H03K5/159

Abstract: A phase-inverted clock generation circuit is provided, where sources of a first PMOS and a second PMOS are connected to a power source, drains of the first PMOS and the second PMOS are connected to a source of a third PMOS, and a drain of the third PMOS is connected to a drain of a third NMOS; and the drain of the third PMOS is connected to a drain of a second NMOS, a source of the second NMOS is connected to a drain of a first NMOS, and a source of the first NMOS and a source of the third NMOS.

公开(公告)号：US11088032B2

公开(公告)日：2021-08-10

申请号：US16239401

申请日：2019-01-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wen Yang ,  Riqing Zhang ,  Yu Xia

IPC: H01L21/8238 ,  H01L29/778 ,  H01L21/265 ,  H01L29/739 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L27/092 ,  H01L29/24

Abstract: In embodiments of the present disclosure, an ambient medium of a two-dimensional semiconductor is doped or an ambient medium of a semiconductor is locally filled with a solid material, to form a filled region, and an electronic device based on the two-dimensional semiconductor is implemented by means of a doping effect of the doped region or the filled region on a characteristic of the two-dimensional semiconductor. In the embodiments of the present disclosure, doping the two-dimensional semiconductor is not directly processing the two-dimensional semiconductor. Therefore, damage caused to the two-dimensional semiconductor in a doping process and device performance deterioration caused accordingly can be effectively reduced, and stability of device performance after doping is improved.

公开(公告)号：US20190139835A1

公开(公告)日：2019-05-09

申请号：US16239401

申请日：2019-01-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wen Yang ,  Riqing Zhang ,  Yu Xia

IPC: H01L21/8238 ,  H01L21/265 ,  H01L27/092 ,  H01L21/02

Abstract: In embodiments of the present disclosure, an ambient medium of a two-dimensional semiconductor is doped or an ambient medium of a semiconductor is locally filled with a solid material, to form a filled region, and an electronic device based on the two-dimensional semiconductor is implemented by means of a doping effect of the doped region or the filled region on a characteristic of the two-dimensional semiconductor. In the embodiments of the present disclosure, doping the two-dimensional semiconductor is not directly processing the two-dimensional semiconductor. Therefore, damage caused to the two-dimensional semiconductor in a doping process and device performance deterioration caused accordingly can be effectively reduced, and stability of device performance after doping is improved.

公开(公告)号：US20180062387A1

公开(公告)日：2018-03-01

申请号：US15687252

申请日：2017-08-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Mei Li ,  Bingwu Ji ,  Yu Xia

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0292

Abstract: This application discloses an electrostatic discharge protection apparatus and an integrated circuit with multiple power domains. The electrostatic discharge protection apparatus includes a diode and an NMOS transistor. A positive electrode of the diode is coupled to a first interface, a negative electrode of the diode is coupled to a first electrode of the NMOS transistor, both a second electrode of the NMOS transistor and a gate electrode of the NMOS transistor are coupled to a second interface, and a substrate of the NMOS transistor is used for grounding. At least one electrostatic discharge protection apparatus may be disposed in the integrated circuit with multiple power domains.