公开(公告)号：US09905159B2

公开(公告)日：2018-02-27

申请号：US14440219

申请日：2013-10-30

Applicant: IMEC VZW ,  Nederlandse Organisatie voor Toegepast-Natuurwetenschappelijk Onderzoek TNO

Inventor： Jan Genoe

IPC: G09G3/3225 ,  G09G3/20 ,  G09G3/3233 ,  G09G3/3258 ,  G09G3/3266 ,  G02F1/13 ,  G09G3/36

CPC classification number: G09G3/3225 ,  G02F1/13 ,  G09G3/2003 ,  G09G3/2018 ,  G09G3/2025 ,  G09G3/3233 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/36 ,  G09G3/3648 ,  G09G2300/08 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2320/0247 ,  G09G2320/043 ,  G09G2330/02

Abstract: A method for digital driving of an active matrix display with a predetermined frame rate is described. The display contains a plurality of pixels organized in a plurality of rows and a plurality of columns. The method includes representing each of the plurality of pixels of an image to be displayed within a frame by an n-bit digital image code. The method also includes dividing the image frame into sub-frames, which may be of substantially equal duration. Within each sub-frame, the method includes sequentially selecting at least one of the plurality of rows twice. Upon a first selection, a first digital code is written to the selected row and upon a second selection a second digital code is written to the selected row. There is a predetermined time delay between the second selection and the first selection. Digital driving circuitry is also described.

公开(公告)号：US09870757B2

公开(公告)日：2018-01-16

申请号：US14647250

申请日：2013-11-25

Applicant: IMEC VZW ,  Nederlandse Organisatie voor Toegepast-Natuurwetenschappelijk Onderzoek TNO

Inventor： Jan Genoe

IPC: G09G5/18 ,  G09G3/32 ,  G09G3/3283

CPC classification number: G09G5/18 ,  G09G3/3283 ,  G09G2300/0852 ,  G09G2320/0693 ,  G09G2330/021

Abstract: Digital driving circuitry for driving an active matrix display comprising a plurality of pixels logically organized in a plurality of rows and a plurality of columns, each pixel comprising a light emitting element, comprises a current driver for each of the plurality of columns for driving a predetermined current through the corresponding column, the predetermined current being proportional to the number of pixels that are ON in that column. The digital driving circuitry further comprises digital select line driving circuitry for sequentially selecting the plurality of rows, and digital data line driving circuitry for writing digital image codes to the pixels in a selected row, synchronized with the digital select line driving circuitry.

公开(公告)号：US09553586B2

公开(公告)日：2017-01-24

申请号：US14565316

申请日：2014-12-09

Applicant: IMEC VZW

Inventor： Jan Genoe ,  Soeren Steudel ,  Zsolt Tokei

IPC: H03K19/0185 ,  H03K17/693 ,  G06F9/455 ,  H03K19/177 ,  H01L27/06 ,  H01L27/108

CPC classification number: H03K19/018585 ,  H01L27/0688 ,  H01L27/10873 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H03K19/1776 ,  H03K19/17796

Abstract: A Field-Programmable Gate Array device is provided with programmable interconnect points in the form of interconnect circuits comprising one or more pass transistors, wherein at least some components of the interconnect circuits are implemented in the Back-End-Of-Line part of the Field-Programmable Gate Array device's production process. The memory element in an interconnect point is not produced as a Static Random Access Memory cell, but as a Dynamic Random Access Memory cell, requiring only a single select transistor and a storage capacitor for each memory element. The fabrication of at least the select transistor and the pass transistor involves the use of a thin film semiconductor layer, e.g., Indium Gallium Zinc Oxide, enabling production of transistors with low leakage in the Back-End-Of-Line.

Abstract translation: 现场可编程门阵列器件提供有包括一个或多个传输晶体管的互连电路形式的可编程互连点，其中互连电路的至少一些部件被实现在场的后端部分 - 可编程门阵列器件的生产工艺。 互连点中的存储元件不是作为静态随机存取存储器单元产生的，而是作为动态随机存取存储器单元，仅对每个存储元件仅需要一个选择晶体管和存储电容器。 至少选择晶体管和传输晶体管的制造涉及使用诸如铟镓锌氧化物的薄膜半导体层，使得能够在后端在线生产具有低泄漏的晶体管。

公开(公告)号：US20150162913A1

公开(公告)日：2015-06-11

申请号：US14565316

申请日：2014-12-09

Applicant: IMEC VZW

Inventor： Jan Genoe ,  Soeren Steudel ,  Zsolt Tokei

IPC: H03K19/0185

CPC classification number: H03K19/018585 ,  H01L27/0688 ,  H01L27/10873 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H03K19/1776 ,  H03K19/17796

Abstract: A Field-Programmable Gate Array device is provided with programmable interconnect points in the form of interconnect circuits comprising one or more pass transistors, wherein at least some components of the interconnect circuits are implemented in the Back-End-Of-Line part of the Field-Programmable Gate Array device's production process. The memory element in an interconnect point is not produced as a Static Random Access Memory cell, but as a Dynamic Random Access Memory cell, requiring only a single select transistor and a storage capacitor for each memory element. The fabrication of at least the select transistor and the pass transistor involves the use of a thin film semiconductor layer, e.g., Indium Gallium Zinc Oxide, enabling production of transistors with low leakage in the Back-End-Of-Line.

Abstract translation: 现场可编程门阵列器件提供有包括一个或多个传输晶体管的互连电路形式的可编程互连点，其中互连电路的至少一些部件被实现在场的后端部分 - 可编程门阵列器件的生产工艺。 互连点中的存储元件不是作为静态随机存取存储器单元产生的，而是作为动态随机存取存储器单元，仅对每个存储元件仅需要一个选择晶体管和存储电容器。 至少选择晶体管和传输晶体管的制造涉及使用诸如铟镓锌氧化物的薄膜半导体层，使得能够在后端在线生产具有低泄漏的晶体管。

公开(公告)号：US11847944B2

公开(公告)日：2023-12-19

申请号：US16972838

申请日：2019-06-03

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Jan Genoe ,  Xavier Rottenberg

IPC: G09G3/00 ,  G09G3/20 ,  G03H1/04

CPC classification number: G09G3/003 ,  G09G3/2085 ,  G03H1/04 ,  G09G3/20 ,  G09G2310/0213 ,  G09G2310/0297

Abstract: A system and for distributing data for 3D light field projection and a method thereof. The system comprises input terminals and output terminals that are connectable to pixel elements of a display. Data paths are established between input terminals and output terminals, and are controlled by data switches. The system also comprises a control plane adapted for applying control variables to the data switches. Control switches of the control plane select the control variables which are applied to the data switches. Sequences of control variables and enable variables propagate along at least one first delay line and along at least one second delay line, respectively. Delay units of the at least one first delay line and of the at least one second delay line have a synchronous relationship. During system run-time patterns contained in the stream of input data are detected for determining the sequences of control variables.

公开(公告)号：US11758294B2

公开(公告)日：2023-09-12

申请号：US17814614

申请日：2022-07-25

Applicant: IMEC VZW

Inventor： Joo Hyoung Kim ,  Jiwon Lee ,  Jan Genoe ,  Robert Gehlhaar

IPC: H04N25/13

CPC classification number: H04N25/135

Abstract: Example embodiments relate to imaging systems and methods for acquisition of multi-spectral images. One example imaging system includes a detector that includes an array of light sensitive elements arranged in rows and columns. Each light sensitive element is configured to generate a signal dependent on an intensity of light incident onto the light sensitive element. The imaging system also includes a plurality of wavelength separating units. Each wavelength separating unit is configured to spatially separate incident light within a wavelength range into a number of wavelength bands distributed along a line. The line is a straight line. Each wavelength band along the line is associated with a mutually unique light sensitive element. Further, the imaging system includes a processing unit configured to define a number of mutually unique clusters of light sensitive elements for summing signals from the light sensitive elements within the respective clusters.

公开(公告)号：US20230030069A1

公开(公告)日：2023-02-02

申请号：US17814614

申请日：2022-07-25

Applicant: IMEC VZW

Inventor： Joo Hyoung Kim ,  Jiwon Lee ,  Jan Genoe ,  Robert Gehlhaar

IPC: H04N9/04

Abstract: Example embodiments relate to imaging systems and methods for acquisition of multi-spectral images. One example imaging system includes a detector that includes an array of light sensitive elements arranged in rows and columns. Each light sensitive element is configured to generate a signal dependent on an intensity of light incident onto the light sensitive element. The imaging system also includes a plurality of wavelength separating units. Each wavelength separating unit is configured to spatially separate incident light within a wavelength range into a number of wavelength bands distributed along a line. The line is a straight line. Each wavelength band along the line is associated with a mutually unique light sensitive element. Further, the imaging system includes a processing unit configured to define a number of mutually unique clusters of light sensitive elements for summing signals from the light sensitive elements within the respective clusters.

公开(公告)号：US20220201821A1

公开(公告)日：2022-06-23

申请号：US17546718

申请日：2021-12-09

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Lynn Verschueren ,  Kris Myny ,  Jan Genoe ,  Wim Dehaene ,  Wim Van Eessen ,  Patrick Willem

IPC: H05B45/397 ,  G09G3/32 ,  H05B45/44

Abstract: A pixel circuit for driving a light-emitting diode (LED) comprises a current-mirror, comprising a primary current path and a secondary current path, arranged to mirror a current through the primary current path to the secondary current path. The current through the primary current path is settable by switching a reference current into the primary current path through a reference current line. The secondary current path is configured to drive the LED. The pixel circuit also includes a switch component arranged to switch the LED to and from the secondary current path based on one or more switch control lines.

公开(公告)号：US20220199002A1

公开(公告)日：2022-06-23

申请号：US17554929

申请日：2021-12-17

Applicant: Imec vzw ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Lynn Verschueren ,  Kris Myny ,  Jan Genoe ,  Wim Dehaene

IPC: G09G3/32

Abstract: A compensated current mirror circuit comprises a current mirror with a primary current path and a secondary current path, configured to mirror a current through the primary current path to the secondary current path. The current is settable by switching a reference current through a reference current line into the primary current path. A primary current mirror transistor is connected in series with the primary current path. A secondary current mirror transistor is connected in series with the secondary current path. A gate of the primary current mirror transistor is connected to a gate of the secondary current mirror transistor at a current mirror node. A compensation block is connected to a back gate of the secondary current mirror transistor and to one or more compensation control lines, and is configured to apply a compensation signal at the back gate based on the compensation control lines.