公开(公告)号：US20210192327A1

公开(公告)日：2021-06-24

申请号：US17131783

申请日：2020-12-23

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Shih-Chieh Chang ,  Shyh-Shyuan Sheu ,  Jian-Wei Su ,  Fu-Cheng Tsai

IPC: G06N3/063 ,  G06N3/04

Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

公开(公告)号：US11741189B2

公开(公告)日：2023-08-29

申请号：US18155762

申请日：2023-01-18

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G11C11/412 ,  G06F17/16

CPC classification number: G06F17/16 ,  G11C11/412

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

公开(公告)号：US20210397675A1

公开(公告)日：2021-12-23

申请号：US17013646

申请日：2020-09-06

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G06F17/16 ,  G11C11/412

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

公开(公告)号：US20210257017A1

公开(公告)日：2021-08-19

申请号：US16850016

申请日：2020-04-16

Applicant: Industrial Technology Research Institute

Inventor： Fu-Cheng Tsai ,  Heng-Yuan Lee ,  Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4099 ,  G11C11/56

Abstract: A computation operator in memory and an operation method thereof are provided. The computation operator in memory includes a word line calculator, a decision-maker and a sense amplifier. The word line calculator calculates a number of enabled word lines of a memory. The decision-maker generates a plurality of reference signals according to at least one of the number of enabled word lines and a used size of the memory, the reference signals are configured to set a distribution range. The sense amplifier receives a readout signal of the memory, and obtains a computation result by converting the readout signal according to the reference signals.