公开(公告)号：US20140264767A1

公开(公告)日：2014-09-18

申请号：US13829582

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Achim Gratz ,  Thimo Schindelar

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer has a number of IC areas and a kerf area arranged between the IC areas. The kerf area has a dicing area, a crack stop structure arranged between an IC area and a dicing area, and a trench arranged between the crack stop structure and the dicing area. The crack stop structure includes an extended layer extending beyond the crack stop structure towards the dicing area.

Abstract translation: 晶片具有多个IC区域和布置在IC区域之间的切口区域。 切口区域具有切割区域，布置在IC区域和切割区域之间的裂纹停止结构以及布置在裂缝停止结构和切割区域之间的沟槽。 裂纹停止结构包括延伸超过裂缝停止结构朝向切割区域延伸的层。

公开(公告)号：US20140232001A1

公开(公告)日：2014-08-21

申请号：US13770639

申请日：2013-02-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Achim Gratz ,  Scott David Wallace ,  Tobias Jacobs

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/94 ,  H01L21/768 ,  H01L21/78 ,  H01L22/34 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/562 ,  H01L23/585 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0382 ,  H01L2224/0392 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00

Abstract: A semiconductor die includes a semiconductor substrate having an edge region surrounding an active region, the active region containing devices of an integrated circuit. The semiconductor die further includes interconnect wiring over the active region in an interlayer dielectric and electrically connected to the devices in the active region, and ancillary wiring over the edge region in the interlayer dielectric and isolated from the interconnect wiring and the devices in the active device region. The interlayer dielectric is passivated, and bond pads are provided over the interconnect wiring and electrically connected to the interconnect wiring through openings in the passivation over the active region. Additional bond pads are provided over the ancillary wiring and are electrically connected to the interconnect wiring through additional openings in the passivation over the active region.

Abstract translation: 半导体管芯包括具有围绕有源区域的边缘区域的半导体衬底，该有源区域包含集成电路的器件。 半导体管芯还包括在层间电介质中的有源区上并且与有源区中的器件电连接的互连布线，以及在层间电介质中的边缘区域上的辅助布线，并且与互连布线和有源器件中的器件隔离 地区。 层间电介质被钝化，并且接合焊盘设置在互连布线之上，并通过激活区域上的钝化中的开口电连接到互连布线。 附加的接合焊盘设置在辅助布线之上，并且通过激活区域上的钝化中的附加开口电连接到互连布线。