公开(公告)号：US10032591B2

公开(公告)日：2018-07-24

申请号：US15333231

申请日：2016-10-25

Applicant: Infineon Technologies AG

Inventor： Achim Gratz

IPC: H01H85/36 ,  H01H85/02 ,  H01H85/54 ,  H01H85/30

Abstract: A fuse arrangement, including: at least a first terminal, a second terminal, and a fuse, wherein the first terminal and the second terminal may be electrically connected via the fuse, and wherein the fuse may be configured to be under fuse internal mechanical stress to deform the fuse along its width direction in case it is broken.

公开(公告)号：US09524844B2

公开(公告)日：2016-12-20

申请号：US13945945

申请日：2013-07-19

Applicant: Infineon Technologies AG

Inventor： Achim Gratz

IPC: H01H85/54 ,  H01H85/143 ,  H01H85/36 ,  H01H85/30 ,  H01H85/02

CPC classification number: H01H85/36 ,  H01H85/0241 ,  H01H85/30 ,  H01H85/54 ,  H01H2085/0283

Abstract: A fuse arrangement, including: at least a first terminal, a second terminal, and a fuse, wherein the first terminal and the second terminal may be electrically connected via the fuse, and wherein the fuse may be configured to be under fuse internal mechanical stress to deform the fuse along its width direction in case it is broken.

Abstract translation: 一种保险丝装置，包括：至少第一端子，第二端子和保险丝，其中所述第一端子和所述第二端子可以经由所述保险丝电连接，并且其中所述保险丝可以被配置为处于熔断器内部机械应力 以使熔断器沿其宽度方向变形，以防破裂。

公开(公告)号：US09401343B2

公开(公告)日：2016-07-26

申请号：US14631206

申请日：2015-02-25

Applicant: Infineon Technologies AG

Inventor： Achim Gratz ,  Scott David Wallace ,  Tobias Jacobs

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L23/58 ,  H01L21/78 ,  H01L21/66

CPC classification number: H01L24/94 ,  H01L21/768 ,  H01L21/78 ,  H01L22/34 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/562 ,  H01L23/585 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0382 ,  H01L2224/0392 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00

Abstract: A method of processing a semiconductor wafer includes forming semiconductor dies in the semiconductor wafer, each die having an active region containing devices of an integrated circuit and an edge region surrounding the active region, adjacent ones of the dies being separated by a scribe line. The method further includes forming interconnect wiring over the active region of each semiconductor die in an interlayer dielectric, forming ancillary wiring over the edge region of each die in the interlayer dielectric, forming a passivation on the interlayer dielectric, forming bond pads over the interconnect wiring of each die, the bond pads of each die being in electrical connection with the interconnect wiring of that die, and forming additional bond pads over the ancillary wiring of each semiconductor die, the additional bond pads of each die being in electrical connection with the interconnect wiring of that die.

Abstract translation: 一种处理半导体晶片的方法包括在半导体晶片中形成半导体管芯，每个管芯具有包含集成电路的器件的有源区域和围绕有源区域的边缘区域，相邻的一个管芯被划线分开。 该方法还包括在层间电介质中在每个半导体管芯的有源区上形成互连布线，在层间电介质的每个管芯的边缘区域上形成辅助布线，在层间电介质上形成钝化，在互连布线上形成接合焊盘 每个管芯的接合焊盘与该管芯的互连布线电连接，并且在每个半导体管芯的辅助布线上形成附加接合焊盘，每个管芯的附加接合焊盘与互连电连接 那个模具的接线。

公开(公告)号：US09299712B2

公开(公告)日：2016-03-29

申请号：US14576463

申请日：2014-12-19

Applicant: Infineon Technologies AG

Inventor： Georg Tempel ,  Ernst-Otto Andersen ,  Achim Gratz

IPC: H01L29/76 ,  H01L27/115 ,  H01L21/28 ,  H01L49/02 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/768 ,  H01L23/535 ,  H01L28/60 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

Abstract translation: 公开了制造半导体器件的半导体器件和方法。 提供半导体本体，浮置栅极多晶硅和源极/漏极区域。 提供了具有控制栅极节点的金属互连区域，其电容耦合到浮动栅极聚合物。

公开(公告)号：US20150179606A1

公开(公告)日：2015-06-25

申请号：US14631206

申请日：2015-02-25

Applicant: Infineon Technologies AG

Inventor： Achim Gratz ,  Scott David Wallace ,  Tobias Jacobs

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/58 ,  H01L21/78 ,  H01L21/768

CPC classification number: H01L24/94 ,  H01L21/768 ,  H01L21/78 ,  H01L22/34 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/562 ,  H01L23/585 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0382 ,  H01L2224/0392 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00

Abstract: A method of processing a semiconductor wafer includes forming semiconductor dies in the semiconductor wafer, each die having an active region containing devices of an integrated circuit and an edge region surrounding the active region, adjacent ones of the dies being separated by a scribe line. The method further includes forming interconnect wiring over the active region of each semiconductor die in an interlayer dielectric, forming ancillary wiring over the edge region of each die in the interlayer dielectric, forming a passivation on the interlayer dielectric, forming bond pads over the interconnect wiring of each die, the bond pads of each die being in electrical connection with the interconnect wiring of that die, and forming additional bond pads over the ancillary wiring of each semiconductor die, the additional bond pads of each die being in electrical connection with the interconnect wiring of that die.

Abstract translation: 一种处理半导体晶片的方法包括在半导体晶片中形成半导体管芯，每个管芯具有包含集成电路的器件的有源区域和围绕有源区域的边缘区域，相邻的一个管芯被划线分开。 该方法还包括在层间电介质中在每个半导体管芯的有源区上形成互连布线，在层间电介质的每个管芯的边缘区域上形成辅助布线，在层间电介质上形成钝化，在互连布线上形成接合焊盘 每个管芯的接合焊盘与该管芯的互连布线电连接，并且在每个半导体管芯的辅助布线上形成附加接合焊盘，每个管芯的附加接合焊盘与互连电连接 那个模具的接线。

公开(公告)号：US08970008B2

公开(公告)日：2015-03-03

申请号：US13829582

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Achim Gratz ,  Thimo Schindelar

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer has a number of IC areas and a kerf area arranged between the IC areas. The kerf area has a dicing area, a crack stop structure arranged between an IC area and a dicing area, and a trench arranged between the crack stop structure and the dicing area. The crack stop structure includes an extended layer extending beyond the crack stop structure towards the dicing area.

Abstract translation: 晶片具有多个IC区域和布置在IC区域之间的切口区域。 切口区域具有切割区域，布置在IC区域和切割区域之间的裂纹停止结构以及布置在裂缝停止结构和切割区域之间的沟槽。 裂纹停止结构包括延伸超过裂缝停止结构朝向切割区域延伸的层。

公开(公告)号：US20150022310A1

公开(公告)日：2015-01-22

申请号：US13945945

申请日：2013-07-19

Applicant: Infineon Technologies AG

Inventor： Achim Gratz

IPC: H01H85/54 ,  H01H85/143

CPC classification number: H01H85/36 ,  H01H85/0241 ,  H01H85/30 ,  H01H85/54 ,  H01H2085/0283

Abstract: A fuse arrangement, including: at least a first terminal, a second terminal, and a fuse, wherein the first terminal and the second terminal may be electrically connected via the fuse, and wherein the fuse may be configured to be under fuse internal mechanical stress to deform the fuse along its width direction in case it is broken.

Abstract translation: 一种保险丝装置，包括：至少第一端子，第二端子和保险丝，其中所述第一端子和所述第二端子可以经由所述保险丝电连接，并且其中所述保险丝可以被配置为处于熔断器内部机械应力 以使熔断器沿其宽度方向变形，以防破裂。

公开(公告)号：US20170040137A1

公开(公告)日：2017-02-09

申请号：US15333231

申请日：2016-10-25

Applicant: Infineon Technologies AG

Inventor： Achim Gratz

IPC: H01H85/36 ,  H01H85/02 ,  H01H85/54 ,  H01H85/30

CPC classification number: H01H85/36 ,  H01H85/0241 ,  H01H85/30 ,  H01H85/54 ,  H01H2085/0283

Abstract: A fuse arrangement, including: at least a first terminal, a second terminal, and a fuse, wherein the first terminal and the second terminal may be electrically connected via the fuse, and wherein the fuse may be configured to be under fuse internal mechanical stress to deform the fuse along its width direction in case it is broken.

Abstract translation: 一种保险丝装置，包括：至少第一端子，第二端子和保险丝，其中所述第一端子和所述第二端子可以经由所述保险丝电连接，并且其中所述保险丝可以被配置为处于熔断器内部机械应力 以使熔断器沿其宽度方向变形，以防破裂。

公开(公告)号：US20150129950A1

公开(公告)日：2015-05-14

申请号：US14576463

申请日：2014-12-19

Applicant: Infineon Technologies AG

Inventor： Georg Tempel ,  Ernst-Otto Andersen ,  Achim Gratz

IPC: H01L27/115 ,  H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/768 ,  H01L23/535 ,  H01L28/60 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

公开(公告)号：US08994148B2

公开(公告)日：2015-03-31

申请号：US13770639

申请日：2013-02-19

Applicant: Infineon Technologies AG

Inventor： Achim Gratz ,  Scott David Wallace ,  Tobias Jacobs

IPC: H01L23/544 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L24/94 ,  H01L21/768 ,  H01L21/78 ,  H01L22/34 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/562 ,  H01L23/585 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0382 ,  H01L2224/0392 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00

Abstract: A semiconductor die includes a semiconductor substrate having an edge region surrounding an active region, the active region containing devices of an integrated circuit. The semiconductor die further includes interconnect wiring over the active region in an interlayer dielectric and electrically connected to the devices in the active region, and ancillary wiring over the edge region in the interlayer dielectric and isolated from the interconnect wiring and the devices in the active device region. The interlayer dielectric is passivated, and bond pads are provided over the interconnect wiring and electrically connected to the interconnect wiring through openings in the passivation over the active region. Additional bond pads are provided over the ancillary wiring and are electrically connected to the interconnect wiring through additional openings in the passivation over the active region.

Abstract translation: 半导体管芯包括具有围绕有源区域的边缘区域的半导体衬底，该有源区域包含集成电路的器件。 半导体管芯还包括在层间电介质中的有源区上并且与有源区中的器件电连接的互连布线，以及在层间电介质中的边缘区域上的辅助布线，并且与互连布线和有源器件中的器件隔离 地区。 层间电介质被钝化，并且接合焊盘设置在互连布线之上，并通过激活区域上的钝化中的开口电连接到互连布线。 附加的接合焊盘设置在辅助布线之上，并且通过激活区域上的钝化中的附加开口电连接到互连布线。