公开(公告)号：US20240332241A1

公开(公告)日：2024-10-03

申请号：US18744174

申请日：2024-06-14

申请人： SK hynix Inc.

发明人： Jin Woong KIM ,  Mi Seon LEE

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L24/30 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05186 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/14134 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2746 ,  H01L2224/29012 ,  H01L2224/29035 ,  H01L2224/29147 ,  H01L2224/29186 ,  H01L2224/3003 ,  H01L2224/30051 ,  H01L2224/3015 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/30517 ,  H01L2224/30519 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/81201 ,  H01L2224/83048 ,  H01L2224/83201 ,  H01L2924/04941 ,  H01L2924/05042

摘要： A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.

公开(公告)号：US20240321702A1

公开(公告)日：2024-09-26

申请号：US18474166

申请日：2023-09-25

申请人： Advanced Micro Devices, Inc. ,  Xilinx, Inc.

发明人： Yan Wang ,  Kevin Gillespie ,  Samuel Naffziger ,  Richard Schultz ,  Raja Swaminathan ,  Omar Zia ,  John Wuu

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC分类号： H01L23/49822 ,  H01L23/3675 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/32 ,  H01L25/0652 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/32146 ,  H01L2224/32165 ,  H01L2924/1431 ,  H01L2924/1437 ,  H01L2924/351

摘要： A method for providing backside power can include providing a first circuit die having a first metal stack. The method can also include connecting a second metal stack of a second circuit die to the first metal stack of the first circuit die, wherein a backside power delivery network is located in a passivation layer of at least one of the first circuit die or the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240304556A1

公开(公告)日：2024-09-12

申请号：US18503950

申请日：2023-11-07

申请人： INSTITUTE OF SEMICONDUCTORS, GUANGDONG ACADEMY OF SCIENCES

发明人： Xun XIANG ,  Chuan HU ,  Yingqiang YAN ,  Yunzhi LING ,  Zhikuan CHEN ,  Zhitao CHEN

IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/5381 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/29 ,  H01L25/0655 ,  H01L2224/05005 ,  H01L2224/05025 ,  H01L2224/29009 ,  H01L2224/29026 ,  H01L2924/10253 ,  H01L2924/18161 ,  H01L2924/18162

摘要： Disclosed is a method of manufacturing a chiplet-fine-interconnection-package structure, comprising: mounting at least two chips on a first side surface of a substrate and preparing a temporary bonding layer on the chips, preparing a plastic package layer on a second side surface of the substrate, wherein the substrate is prepared with microvias to allow plastic package materials to flow from the microvias into an area between the first side surface of the substrate and the temporary bonding layer to prepare the plastic package layer; releasing the temporary bonding layer, and bonding a silicon bridge structure on the first pin-arrays of the two adjacent chips. The solution provided by the present invention makes it unnecessary to remove the substrate in the subsequent process and to perform grinding and thinning process on the corresponding position of the plastic package layer, thus simplifying the packaging process steps and reducing the packaging cost.

公开(公告)号：US11999001B2

公开(公告)日：2024-06-04

申请号：US17545322

申请日：2021-12-08

申请人： Adeia Semiconductor Technologies LLC

发明人： Cyprian Emeka Uzoh

IPC分类号： H05K1/11 ,  B23K20/00 ,  B23K20/02 ,  H01L21/50 ,  H01L23/00 ,  H01L23/10 ,  H01L23/48 ,  H01L23/49 ,  H01L23/498 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H05K13/04 ,  H01L21/48 ,  H01L21/768

CPC分类号： B23K20/023 ,  B23K20/002 ,  H01L21/50 ,  H01L23/10 ,  H01L23/481 ,  H01L23/49 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/98 ,  H05K1/11 ,  H05K1/14 ,  H05K1/144 ,  H05K1/18 ,  H05K3/0094 ,  H05K3/34 ,  H05K13/046 ,  H05K13/0465 ,  H01L21/4853 ,  H01L21/76898 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/27 ,  H01L2224/02372 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05138 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13009 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/1319 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16501 ,  H01L2224/16503 ,  H01L2224/16505 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/29023 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29138 ,  H01L2224/29147 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81075 ,  H01L2224/8112 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81825 ,  H01L2224/83075 ,  H01L2224/8312 ,  H01L2224/83193 ,  H01L2224/83825 ,  H01L2924/00014 ,  H01L2924/381 ,  H05K1/111 ,  H05K2201/04 ,  H05K2203/04 ,  H01L2224/8112 ,  H01L2924/00014 ,  H01L2224/1147 ,  H01L2924/00014 ,  H01L2224/05187 ,  H01L2924/04953 ,  H01L2224/0518 ,  H01L2924/01071 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05181 ,  H01L2924/00014 ,  H01L2224/05171 ,  H01L2924/01042 ,  H01L2224/05138 ,  H01L2924/01015 ,  H01L2924/00014 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05164 ,  H01L2924/00014 ,  H01L2224/05187 ,  H01L2924/04941 ,  H01L2224/05155 ,  H01L2924/01015 ,  H01L2224/05157 ,  H01L2924/01015 ,  H01L2224/05166 ,  H01L2924/01074 ,  H01L2224/05155 ,  H01L2924/01074 ,  H01L2224/13105 ,  H01L2924/01047 ,  H01L2224/13109 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2224/13138 ,  H01L2924/01034 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/11464 ,  H01L2924/00014 ,  H01L2224/1145 ,  H01L2924/00014 ,  H01L2224/11452 ,  H01L2924/00014 ,  H01L2224/16501 ,  H01L2924/00012 ,  H01L2224/16505 ,  H01L2924/00012 ,  H01L2224/14131 ,  H01L2924/00014 ,  H01L2224/05026 ,  H01L2924/00012 ,  H01L2224/05571 ,  H01L2924/00012 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/13184 ,  H01L2924/00014 ,  H01L2224/73103 ,  H01L2924/00012 ,  H01L2224/73203 ,  H01L2924/00012 ,  H01L2224/27462 ,  H01L2924/00014 ,  H01L2224/27464 ,  H01L2924/00014 ,  H01L2224/2745 ,  H01L2924/00014 ,  H01L2224/27452 ,  H01L2924/00014 ,  H01L2224/29105 ,  H01L2924/01047 ,  H01L2224/29109 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2224/29138 ,  H01L2924/01034 ,  H01L2224/32501 ,  H01L2924/00012 ,  H01L2224/32505 ,  H01L2924/00012 ,  H01L2224/8312 ,  H01L2924/00014 ,  H01L2224/1319 ,  H01L2924/07025 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/13018 ,  H01L2924/00012

摘要： A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element.

公开(公告)号：US11984417B2

公开(公告)日：2024-05-14

申请号：US17648309

申请日：2022-01-19

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Ling-Yi Chuang

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/03 ,  H01L2224/0331 ,  H01L2224/03462 ,  H01L2224/05013 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/05564 ,  H01L2224/05578 ,  H01L2224/05601 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05638 ,  H01L2224/08145 ,  H01L2224/08503 ,  H01L2224/8081

摘要： The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first chip and a second chip. A first conductive connection wire of the first chip is connected to a first conductive contact pad, and a second conductive connection wire of the second chip is connected to a second conductive contact pad. In addition, the first conductive contact pad includes a first conductor group and a second conductor group, and the second conductive contact pad includes a third conductor group and a fourth conductor group.

公开(公告)号：US11984415B2

公开(公告)日：2024-05-14

申请号：US17528954

申请日：2021-11-17

申请人： Samsung Electronics Co., Ltd.

发明人： Yukyung Park ,  Ungcheon Kim ,  Wonil Lee

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/544 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48

CPC分类号： H01L24/02 ,  H01L21/486 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L25/105 ,  H01L25/18 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/04 ,  H01L2223/54426 ,  H01L2224/0213 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03019 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05019 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/0603 ,  H01L2224/06182

摘要： An interposer according to an embodiment of the present invention includes a base layer having opposite first and second surfaces, a wiring structure on the first surface of the base layer, an interposer protective layer disposed on the second surface of the base layer and having a pad recess with a lower surface of the interposer protective layer positioned at a first vertical level and a bottom surface of the pad recess positioned at a second vertical level that is higher than the first vertical level, an interposer pad of which a portion fills the pad recess of the interposer protective layer and the remaining portion protrudes from the interposer protective layer, and an interposer through electrode extending through the base layer and the interposer protective layer to the interposer pad, the interposer through electrode electrically connecting the wiring structure to the interposer pad.

公开(公告)号：US20240079271A1

公开(公告)日：2024-03-07

申请号：US18273647

申请日：2021-11-23

申请人： CHIPMORE TECHNOLOGY CORPORATION LIMITED ,  HEFEI CHIPMORE TECHNOLOGY CO., LTD.

发明人： Wenjie HUANG

IPC分类号： H01L21/768 ,  H01L21/66 ,  H01L23/00

CPC分类号： H01L21/76895 ,  H01L22/14 ,  H01L24/05 ,  H01L24/19 ,  H01L2224/05025 ,  H01L2224/19

摘要： The present invention discloses a wafer rewiring double verification structure, and a manufacturing method and a verification method thereof, wherein the wafer rewiring double verification structure includes: a die having a substrate, a plurality of pads and a passivation layer; a plurality of rewiring modules; and a gap portion formed between every two adjacent rewiring modules. A dielectric module is disposed on each rewiring module, and is provided with an inclined surface; and an electroplated layer is disposed on the inclined surface. According to the present invention, functional verification can be performed on different rewiring modules on the same wafer in one manufacturing process.

公开(公告)号：US20230369243A1

公开(公告)日：2023-11-16

申请号：US17742541

申请日：2022-05-12

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TSE-YAO HUANG

IPC分类号： H01L23/00

CPC分类号： H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L23/564 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/05025 ,  H01L2924/351

摘要： The present application provides a semiconductor structure having a porous structure between a conductive pad and a metal layer. The semiconductor structure includes: a substrate including an interconnection structure; a dielectric layer disposed over the substrate; a conductive pad disposed over the dielectric layer; a passivation layer, disposed over the dielectric layer and partially exposing the conductive pad; and a porous layer, surrounded by the dielectric layer and extending between the substrate and the conductive pad.

公开(公告)号：US20230253306A1

公开(公告)日：2023-08-10

申请号：US18303557

申请日：2023-04-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： TUNG-JIUN WU

IPC分类号： H01L23/522 ,  H01L23/00

CPC分类号： H01L23/5223 ,  H01L24/13 ,  H01L28/40 ,  H01L24/05 ,  H01L2924/19041 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05144 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05124 ,  H01L2224/05164 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13144 ,  H01L2924/19104

摘要： A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a conductive member surrounded by the first dielectric layer; a second dielectric layer disposed over the substrate, the first dielectric layer and the conductive member; a capacitor disposed over the conductive member and the second dielectric layer; a third dielectric layer disposed over the second dielectric layer and the capacitor; a conductive via disposed over and contacted with the conductive member, and extended through the second dielectric layer, the capacitor and the third dielectric layer; a conductive pad disposed over and contacted with the conductive via; a fourth dielectric layer disposed over the third dielectric layer and surrounding the conductive pad; and a conductive bump disposed over and electrically connected to the conductive pad, wherein the third dielectric layer includes an oxide layer and a nitride layer.

公开(公告)号：US20230223323A1

公开(公告)日：2023-07-13

申请号：US17979480

申请日：2022-11-02

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kyungsoo KIM ,  Kyenhee LEE

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L23/538 ,  H01L25/07 ,  H01L23/00

CPC分类号： H01L23/49816 ,  H01L23/481 ,  H01L23/49844 ,  H01L23/5384 ,  H01L25/07 ,  H01L24/16 ,  H01L24/05 ,  H01L2224/16146 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2924/15311

摘要： A semiconductor package is provided. The semiconductor package includes: a first semiconductor chip including a first bonding structure; , a first front-end level layer including a first integrated circuit device; a first sub-back-end level layer including a plurality of first metal wire layers, an input and output device level layer including a two-dimensional input and output device, and a second sub-back-end level layer including a plurality of second metal wire layers electrically connected to the first integrated circuit device and the two-dimensional input and output device. The semiconductor package also includes a second semiconductor chip including a bonding structure that is bonded to the first bonding structure; a second front-end level layer including a second integrated circuit device, and a second back-end level layer including a plurality of third metal wire layers electrically connected to the second integrated circuit device.