公开(公告)号：US20170170646A1

公开(公告)日：2017-06-15

申请号：US15443161

申请日：2017-02-27

Applicant: INTEL CORPORATION

Inventor： Amit Kumar SRIVASTAVA ,  Karthik NS ,  Raghavendra Devappa SHARMA ,  Dharmaray NEDALGI ,  Prasad BHILAWADI

IPC: H02H3/18 ,  G06F1/26 ,  G06F1/32 ,  H04B1/38 ,  H04L25/02

CPC classification number: H02H3/18 ,  G06F1/26 ,  G06F1/3212 ,  H04B1/38 ,  H04L25/0272

Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.

公开(公告)号：US20160233854A1

公开(公告)日：2016-08-11

申请号：US15025231

申请日：2013-11-26

Applicant: INTEL CORPORATION

Inventor： Amit Kumar SRIVASTAVA ,  Chee Seng LEONG

IPC: H03K5/08

CPC classification number: H03K5/08

Abstract: Described is an apparatus which comprises: a sensor to detect entrance of single-ended-zero (SE0) state on first and second data lines, and to detect exit of the SE0 state; and a clamp unit to clamp an overshoot or undershoot condition on the first or second data lines during the detected entrance and exit of the SE0 state.

Abstract translation: 描述了一种装置，其包括：传感器，用于检测第一和第二数据线上的单端零（SE0）状态的入口，并检测SE0状态的退出; 以及钳位单元，用于在检测到的SE0状态的进入和退出期间夹紧第一或第二数据线上的过冲或下冲状态。