公开(公告)号：US20170170646A1

公开(公告)日：2017-06-15

申请号：US15443161

申请日：2017-02-27

Applicant: INTEL CORPORATION

Inventor： Amit Kumar SRIVASTAVA ,  Karthik NS ,  Raghavendra Devappa SHARMA ,  Dharmaray NEDALGI ,  Prasad BHILAWADI

IPC: H02H3/18 ,  G06F1/26 ,  G06F1/32 ,  H04B1/38 ,  H04L25/02

CPC classification number: H02H3/18 ,  G06F1/26 ,  G06F1/3212 ,  H04B1/38 ,  H04L25/0272

Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.