公开(公告)号：US20180091148A1

公开(公告)日：2018-03-29

申请号：US15279273

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Siti Suhaila MOHD YUSOF ,  Amit Kumar SRIVASTAVA ,  Lay Hock KHOO ,  Chin Boon TEAR

IPC: H03K19/00 ,  H03K19/003 ,  G06F1/28 ,  G06F1/06

CPC classification number: H03K19/0005 ,  G06F1/06 ,  G06F1/28 ,  H03K19/00369

Abstract: An apparatus is provided which comprises: a data sampler coupled to an output of a driver, wherein the data sampler is to sample data and to compare it with a first threshold voltage and a second threshold voltage, and wherein the data sampler is to generate an up or down indicator according to comparing the data with the first and second threshold voltages; and logic coupled to the data sampler, wherein the logic is to receive the up or down indicator and to increment or decrement a number of already DC compensated impedance legs of the driver according to the up or down indicator.

公开(公告)号：US20180275713A1

公开(公告)日：2018-09-27

申请号：US15465533

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Amit Kumar SRIVASTAVA

IPC: G06F1/06 ,  G06F1/08 ,  G06F13/42

CPC classification number: G06F13/4291

Abstract: An apparatus is provided which comprises: a data circuitry to send and receive data to and from one or more devices coupled to the data circuitry via a first transmission line; and a first adjustable clock buffer coupled to the data circuitry, wherein the first adjustable clock buffer is to adjust a delay to an edge of a read clock according to a response time of the one or more devices.

公开(公告)号：US20180335830A1

公开(公告)日：2018-11-22

申请号：US15776777

申请日：2016-11-01

Applicant: INTEL CORPORATION

Inventor： Amit Kumar SRIVASTAVA

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3296 ,  G06F1/325 ,  G06F1/3253 ,  G06F13/4282 ,  G06F2213/0042

Abstract: A Universal Serial Bus 2.0 (USB2 or eUSB2) device includes an integrated circuit (IC) having a physical layer to send and receive data on a pair of signal lines, a repeater communicatively coupled to the physical layer via the pair of signal lines, and having a port to send and receive data on a second pair of signal lines and a power management unit to provide power to the physical layer and the repeater during an active state and to gate power to the physical layer and the repeater during a low power state.

公开(公告)号：US20200257601A1

公开(公告)日：2020-08-13

申请号：US15776384

申请日：2016-10-13

Applicant: INTEL CORPORATION

Inventor： Amit Kumar SRIVASTAVA ,  Huimin CHEN

IPC: G06F11/273 ,  G06F11/22 ,  G06F13/42

Abstract: Techniques and mechanisms for exchanging debug information with a repeater and multiplex logic of a platform. In an embodiment, the multiplex logic can be configured to any of multiple modes including a first mode to exchange debug information between the repeater and debug client logic of the platform. Another of the multiple modes may provide an alternate communication path for exchanging functional data, other than any debug information, between the repeater and a physical layer interface of the platform. In another embodiment, the repeater is compatible with a repeater architecture identified by a universal serial bus standard. The physical layer interface is compatible with an interface specification identified by the same universal bus standard.

公开(公告)号：US20190103889A1

公开(公告)日：2019-04-04

申请号：US15721535

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Amit Kumar SRIVASTAVA

IPC: H04B1/04 ,  H04B1/16 ,  G06F13/40 ,  G06F1/30

Abstract: Described is an apparatus which comprises: a driver comprising a push-pull transmitter; a first circuitry to sense variation in a power supply; and a second circuitry coupled to the first circuitry and to the driver, the second circuitry to generate a code according to an output of the first circuitry, wherein the code is provided to the driver to adjust a performance parameter of the driver.

公开(公告)号：US20180364780A1

公开(公告)日：2018-12-20

申请号：US16062093

申请日：2016-11-23

Applicant: INTEL CORPORATION

Inventor： Ramnarayanan MUTHUKARUPPAN ,  Anoop Kumar UPADHYAY ,  Gaurav GOEL ,  Amit Kumar SRIVASTAVA

IPC: G06F1/28 ,  G06F9/445 ,  G06F13/20 ,  G06F13/40

Abstract: A configuration interface bus may be coupled to components of a physical layer (PHY) device. A configuration controller may be coupled with the configuration interface bus and may receive an input signal representing a power state of the PHY device. The configuration controller may further identify a set of instructions that correspond to the input signal and may transmit configuration data via the configuration interface bus to one or more of the components of the PHY device in response to an execution of the set of instructions. The operation of the one or more components of the PHY device may be based on the configuration data.

公开(公告)号：US20170077969A1

公开(公告)日：2017-03-16

申请号：US15276689

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Kang Choong YONG ,  Boon Ping KOH ,  Amit Kumar SRIVASTAVA ,  Wil Choon Song

IPC: H04B1/04

CPC classification number: H04B1/0475 ,  H03F1/34 ,  H03F3/24 ,  H04B1/0483 ,  H04B3/30 ,  H04B15/02 ,  H04B2001/0408 ,  H04B2001/0433 ,  H04B2215/00

Abstract: Described is an apparatus which comprises: a pre-driver coupled to a transmitter, the transmitter having a differential output; and a tuning circuit operable to couple to the differential output to tune the pre-driver of the transmitter according to a common mode noise signature of a common mode signal derived from the differential output.

Abstract translation: 描述了一种装置，包括：耦合到发射机的预驱动器，所述发射机具有差分输出; 以及调谐电路，其可操作以耦合到差分输出端，以根据从差分输出得到的共模信号的共模噪声特征来调谐发射机的预驱动器。

公开(公告)号：US20190189226A1

公开(公告)日：2019-06-20

申请号：US15845683

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Amit Kumar SRIVASTAVA ,  Sriram BALASUBRAHMANYAM

IPC: G11C16/32

CPC classification number: G11C16/32 ,  G11C7/22

Abstract: An apparatus is provided which comprises: a buffer to receive first data from a host, and output the first data with configurable delay; and one or more circuitries to: compare the first data from the host with second data that is accessible to the apparatus, wherein the second data is substantially a copy of the first data, and calibrate the delay of the buffer, based at least in part on the comparison of the first data and the second data.

公开(公告)号：US20190051060A1

公开(公告)日：2019-02-14

申请号：US16019945

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Jagannadha Rao RAPETA ,  Asad AZAM ,  Amit Kumar SRIVASTAVA

IPC: G07C5/00 ,  H04R1/32 ,  H04R29/00 ,  G08B29/12 ,  G07C5/08

Abstract: Methods and apparatus relating to functional safety critical audio system for autonomous and industrial applications are described. In an embodiment, safety island logic circuitry transmits an enable signal to cause initiation of a functional safety test for an audio component in a vehicle. Audio processing logic circuitry receives the enable signal and causes activation of power amplifier logic circuitry, in response to the enable signal, to drive the audio component in accordance with an audio alert test signal. The audio component includes a Parametric Acoustic Array (PAA) transducer. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180287771A1

公开(公告)日：2018-10-04

申请号：US15472145

申请日：2017-03-28

Applicant: Intel Corporation

Inventor： Amit Kumar SRIVASTAVA ,  Chenchu Punnarao BANDI

IPC: H04L7/00 ,  H04L25/20

Abstract: A method and system implements a repeater in a link of a communication medium. The method and system enables a counter to count alternations of a clock signal received from a host or device over the link, compares a value of the counter to a reference count, adjusts a frequency selection based on the comparison of the value of the counter to the reference count, and locks the frequency selection in response to the counter matching the reference count.