公开(公告)号：US20190042944A1

公开(公告)日：2019-02-07

申请号：US16004243

申请日：2018-06-08

Applicant: Intel Corporation

Inventor： Krishnakumar Nair ,  Andrew Yang ,  Brian Morris

IPC: G06N3/08 ,  G06N3/04

Abstract: Thus, the present disclosure is directed to systems and methods for training neural networks using a tensor that includes a plurality of FP16 values and a plurality of bits that define an exponent shared by some or all of the FP16 values included in the tensor. The FP16 values may include IEEE 754 format 16-bit floating point values and the tensor may include a plurality of bits defining the shared exponent. The tensor may include a shared exponent and FP16 values that include a variable bit-length mantissa and a variable bit-length exponent that may be dynamically set by processor circuitry. The tensor may include a shared exponent and FP16 values that include a variable bit-length mantissa; a variable bit-length exponent that may be dynamically set by processor circuitry; and a shared exponent switch set by the processor circuitry to selectively combine the FP16 value exponent with the shared exponent.

公开(公告)号：US20190042094A1

公开(公告)日：2019-02-07

申请号：US16024812

申请日：2018-06-30

Applicant: INTEL CORPORATION

Inventor： Krishnakumar Nair ,  Andrew Yang ,  Michael Rotzn ,  Nitin Garegrat ,  Tom Schebye ,  Tony Werner

IPC: G06F3/06 ,  G06F9/30

Abstract: An apparatus and method for a converting tensor data. For example, one embodiment of a method comprises: fetching source tensor blocks of a source tensor data structure, each source tensor block comprising a plurality of source tensor data elements having a first numeric representation, wherein the source tensor data structure comprises a predefined structural arrangement of source tensor blocks; converting the one or more source tensor blocks into one or more destination tensor blocks comprising a plurality of destination tensor data elements having a second numeric representation different from the first numeric representation, wherein the sets of one or more source tensor blocks are converted to one or more corresponding destination tensor blocks in a specified order based on the first and second numeric representations; and storing each individual destination tensor block in a designated memory region to maintain coherency with the predefined structural arrangement of the source tensor blocks.

公开(公告)号：US20170060811A1

公开(公告)日：2017-03-02

申请号：US14697728

申请日：2015-04-28

Applicant: Intel Corporation

Inventor： Andrew Yang ,  Carey Kloss ,  Prashant Arora ,  Tony Werner ,  Naveen Gandham Rao ,  Amir Khosrowshahi

IPC: G06F17/16 ,  G06N3/08 ,  G06F12/02

CPC classification number: G06F17/16 ,  G06F12/023 ,  G06F2212/251 ,  G06N3/08

Abstract: Described herein are methods, systems, and apparatuses to utilize a matrix operation by accessing each of the operation's matrix operands via a respective single memory handle. This use of a single memory handle for each matrix operand eliminates significant overhead in memory allocation, data tracking, and subroutine complexity present in prior art solutions. The result of the matrix operation can also be accessible via a single memory handle identifying the matrix elements of the result.

Abstract translation: 这里描述了通过经由相应的单个存储器句柄访问每个操作的矩阵操作数来利用矩阵运算的方法，系统和装置。 每个矩阵操作数使用单个存储器句柄消除了现有技术解决方案中存在的内存分配，数据跟踪和子程序复杂度方面的重大开销。 矩阵运算的结果也可以通过识别结果的矩阵元素的单个存储器句柄来访问。

公开(公告)号：US20230222331A1

公开(公告)日：2023-07-13

申请号：US18184651

申请日：2023-03-15

Applicant: Intel Corporation

Inventor： Horce H. Lau ,  Prashant Arora ,  Olivia K. Wu ,  Tony L. Werner ,  Carey K. Kloss ,  Amir Khosrowshahi ,  Andrew Yang ,  Aravind Kalaiah ,  Vijay Anand R. Korthikanti

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/08 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08

Abstract: A network of matrix processing units (MPUs) is provided on a device, where each MPU is connected to at least one other MPU in the network, and each MPU is to perform matrix multiplication operations. Computer memory stores tensor data and a master control central processing unit (MCC) is provided on the device to receive an instruction from a host device, where the instruction includes one or more tensor operands based on the tensor data. The MCC invokes a set of operations on one or more of the MPUs based on the instruction, where the set of operations includes operations on the tensor operands. A result is generated from the set of operations, the result embodied as a tensor value.

公开(公告)号：US20220245438A1

公开(公告)日：2022-08-04

申请号：US17728175

申请日：2022-04-25

Applicant: Intel Corporation

Inventor： Horce H. Lau ,  Prashant Arora ,  Olivia K. Wu ,  Tony L. Werner ,  Carey K. Kloss ,  Amir Khosrowshahi ,  Andrew Yang ,  Aravind Kalaiah ,  Vijay Anand R. Korthikanti

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08

Abstract: A network of matrix processing units (MPUs) is provided on a device, where each MPU is connected to at least one other MPU in the network, and each MPU is to perform matrix multiplication operations. Computer memory stores tensor data and a master control central processing unit (MCC) is provided on the device to receive an instruction from a host device, where the instruction includes one or more tensor operands based on the tensor data. The MCC invokes a set of operations on one or more of the MPUs based on the instruction, where the set of operations includes operations on the tensor operands. A result is generated from the set of operations, the result embodied as a tensor value.

公开(公告)号：US11204766B2

公开(公告)日：2021-12-21

申请号：US16557187

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Jason Seung-Min Kim ,  Nitin N. Garegrat ,  Anitha Loke ,  Nasima Parveen ,  David Y. Fang ,  Kursad Kiziloglu ,  Dmitry Sergeyevich Lukiyanchenko ,  Fabrice Paillet ,  Andrew Yang

IPC: G06F9/30

Abstract: Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.

公开(公告)号：US09886418B2

公开(公告)日：2018-02-06

申请号：US14697728

申请日：2015-04-28

Applicant: Intel Corporation

Inventor： Andrew Yang ,  Carey Kloss ,  Prashant Arora ,  Tony Werner ,  Naveen Gandham Rao ,  Amir Khosrowshahi

IPC: G06F12/00 ,  G06F17/16 ,  G06F12/02 ,  G06N3/08

CPC classification number: G06F17/16 ,  G06F12/023 ,  G06F2212/251 ,  G06N3/08

Abstract: Described herein are methods, systems, and apparatuses to utilize a matrix operation by accessing each of the operation's matrix operands via a respective single memory handle. This use of a single memory handle for each matrix operand eliminates significant overhead in memory allocation, data tracking, and subroutine complexity present in prior art solutions. The result of the matrix operation can also be accessible via a single memory handle identifying the matrix elements of the result.

公开(公告)号：US20170061279A1

公开(公告)日：2017-03-02

申请号：US14597091

申请日：2015-01-14

Applicant: Intel Corporation

Inventor： Andrew Yang ,  Carey Kloss ,  Prashant Arora ,  Alex S. Park ,  Naveen G. Rao ,  Amir Khosrowshahi

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/084

Abstract: Updating an artificial neural network is disclosed. A node characteristic is represented using a fixed point node characteristic parameter. A network characteristic is represented using a fixed point network characteristic parameter. The fixed point node characteristic parameter and the fixed point network characteristic parameter are processed to determine a fixed point intermediate parameter having a larger size than either the fixed point node characteristic parameter or the fixed point network characteristic parameter. A value associated with the fixed point intermediate parameter is truncated according to a system truncation schema. The artificial neural network is updated according to the truncated value.

Abstract translation: 公开了更新人造神经网络。 使用固定点节点特征参数来表示节点特性。 使用固定点网络特性参数表示网络特性。 处理固定点节点特征参数和固定点网络特征参数，以确定具有比固定点节点特征参数或固定点网络特征参数大的大小的固定点中间参数。 与固定点中间参数相关联的值根据系统截断模式被截断。 人工神经网络根据截断值进行更新。