公开(公告)号：US11567555B2

公开(公告)日：2023-01-31

申请号：US16557657

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Jason Seung-Min Kim ,  Sundar Ramani ,  Yogesh Bansal ,  Nitin N. Garegrat ,  Olivia K. Wu ,  Mayank Kaushik ,  Mrinal Iyer ,  Tom Schebye ,  Andrew Yang

IPC: G06F1/324 ,  G06F1/08 ,  G06F1/28 ,  G06F1/12 ,  G06F9/30 ,  G06F9/28 ,  G06N3/08

Abstract: Embodiments include an apparatus comprising an execution unit coupled to a memory, a microcode controller, and a hardware controller. The microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase, and use the first local hint to balance power consumption between the execution unit and the memory during parallel executions of the first and second instruction phases. The hardware controller is to use the global hint to determine an appropriate voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit during the parallel executions of the first and second instruction phases. The first local hint includes a processing rate for the first instruction phase or an indication of the processing rate.

公开(公告)号：US11204766B2

公开(公告)日：2021-12-21

申请号：US16557187

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Jason Seung-Min Kim ,  Nitin N. Garegrat ,  Anitha Loke ,  Nasima Parveen ,  David Y. Fang ,  Kursad Kiziloglu ,  Dmitry Sergeyevich Lukiyanchenko ,  Fabrice Paillet ,  Andrew Yang

IPC: G06F9/30

Abstract: Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.