公开(公告)号：US20190385994A1

公开(公告)日：2019-12-19

申请号：US16007867

申请日：2018-06-13

Applicant: Intel Corporation

Inventor： Michael Rifani ,  Robert J. Munoz ,  Thomas P. Thomas ,  John Mark Matson ,  Kursad Kiziloglu

IPC: H01L25/18 ,  H01L23/32 ,  H01L23/538 ,  G02B6/12

Abstract: Embodiments may relate to a substrate for use in a system in package (SIP). The substrate may include a first couple to couple with a first component via a permanent couple such that the first component is communicatively coupled with a bridge. The substrate may further include a second couple to removably couple with an interposer such that the interposer is communicatively coupled with the bridge via a communicative couple. Other embodiments may be described or claimed.

公开(公告)号：US11251171B2

公开(公告)日：2022-02-15

申请号：US16007867

申请日：2018-06-13

Applicant: Intel Corporation

Inventor： Michael Rifani ,  Robert J. Munoz ,  Thomas P. Thomas ,  John Mark Matson ,  Kursad Kiziloglu

IPC: H01L25/18 ,  H01L23/32 ,  G02B6/12 ,  H01L23/538

Abstract: Embodiments may relate to a substrate for use in a system in package (SIP). The substrate may include a first couple to couple with a first component via a permanent couple such that the first component is communicatively coupled with a bridge. The substrate may further include a second couple to removably couple with an interposer such that the interposer is communicatively coupled with the bridge via a communicative couple. Other embodiments may be described or claimed.

公开(公告)号：US11204766B2

公开(公告)日：2021-12-21

申请号：US16557187

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Jason Seung-Min Kim ,  Nitin N. Garegrat ,  Anitha Loke ,  Nasima Parveen ,  David Y. Fang ,  Kursad Kiziloglu ,  Dmitry Sergeyevich Lukiyanchenko ,  Fabrice Paillet ,  Andrew Yang

IPC: G06F9/30

Abstract: Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.