公开(公告)号：US20220376657A1

公开(公告)日：2022-11-24

申请号：US17323189

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Ofir Degani ,  Assaf Ben-Bassat ,  Ashoke Ravi ,  Ina Shternberg ,  Naor Shay

IPC: H03F1/02 ,  H03F3/21

Abstract: Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.

公开(公告)号：US10958255B1

公开(公告)日：2021-03-23

申请号：US16727958

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Gil Asa ,  Assaf Ben-Bassat ,  Ofir Degani ,  Shahar Gross ,  Rotem Banin ,  Uri Grosglik

IPC: H03K5/00 ,  H03K5/133 ,  H03K5/156 ,  H03K5/1534 ,  G01R31/3177 ,  G01R31/3185

Abstract: This disclosure provides devices and methods for limiting the duration of pulses resulting from frequency modulation so as to provide for better propagation of a frequency doubler output within a communication device. The frequency doubler may be configured to receive a frequency doubler input and produce a modified frequency doubler output, wherein the frequency doubler includes a first flip-flop gate configured to receive a data input, a reset input, and a clock input and produce a first gate output; a first delay control configured to receive the gate output and produce a first delayed control output; and a first logic gate configured to receive the delayed control output and the frequency doubler input and produce a first logic gate output, wherein the modified frequency doubler output is based on the first logic gate output.

公开(公告)号：US09054855B2

公开(公告)日：2015-06-09

申请号：US14047117

申请日：2013-10-07

Applicant: Intel Corporation

Inventor： Assaf Ben-Bassat

IPC: H04L7/04 ,  H04L25/08 ,  H04B7/04

CPC classification number: H04L25/08 ,  H04B7/0413 ,  H04B7/0617 ,  H04L7/06 ,  H04L25/0276

Abstract: Embodiments of a system and method for synchronizing chains in a transceiver using central synchronization signals are generally described herein. In some embodiments, an RF signal having a reference frequency in a differential mode and a synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are produced at a oscillator generation circuit. The RF signal having a reference frequency in a differential mode and the synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are provided over each of a plurality of LO lines to a plurality of local LO generation circuit chains. Each synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode is extracted at the plurality of local LO generation circuit chains. A phase of each RF signal having a reference frequency in a differential mode is synchronized in each of the plurality of local LO generation circuit chains using each extracted synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode.

Abstract translation: 这里一般地描述使用中央同步信号在收发机中同步链的系统和方法的实施例。 在一些实施例中，在振荡器产生电路处产生具有差分模式的参考频率的RF信号和具有以公共模式除以整数的参考频率的第二频率的同步信号。 具有差分模式的参考频率的RF信号和具有以公共模式除以整数的参考频率的第二频率的同步信号在多个LO线中的每一个上被提供给多个本地LO生成电路链 。 在多个本地LO产生电路链中提取具有以公共模式除以整数的参考频率的第二频率的每个同步信号。 使用每个提取出的同步信号，在多个本地LO生成电路链中的每一个中，将具有差分模式的参考频率的每个RF信号的相位同步，其中第二频率是基准频率除以共模的整数。