公开(公告)号：US12021608B2

公开(公告)日：2024-06-25

申请号：US17763642

申请日：2019-12-26

Applicant: INTEL CORPORATION

Inventor： Ofir Degani ,  Ehud Reshef ,  Eytan Mann ,  Ashoke Ravi

IPC: H04B7/24 ,  H04B7/0413

CPC classification number: H04B7/24 ,  H04B7/0413

Abstract: Some demonstrative embodiments may include an apparatus including an integrated Radio Head (RH), the integrated RH including an antenna; a transceiver chain to transmit a Radio Frequency (RF) transmit (Tx) signal via the antenna, and to receive an RF Receive (Rx) signal via the antenna; a Physical layer (PHY) time-domain (TD) processor configured to generate a digital PHY TD Rx signal based on the RF Rx signal, and to cause the transceiver chain to transmit the RF Tx signal based on a digital PHY TD Tx signal; and a digital interface to communicate the digital PHY TD Tx signal and the digital PHY TD Rx signal over a digital link.

公开(公告)号：US20240171563A1

公开(公告)日：2024-05-23

申请号：US18057303

申请日：2022-11-21

Applicant: Intel Corporation

Inventor： Yoni Kahana ,  Eytan Mann

IPC: H04L9/40

CPC classification number: H04L63/0823 ,  H04L63/0435

Abstract: An architecture is provided that enables a trust on first use (TOFU) scheme to be realized for two modules (such as an SoC and a companion module) that comprise part of a hardware platform. The architecture leverages symmetric encryption schemes and relies upon an initial setup process in a controlled environment, during which time unencrypted communications may initially be used until the SoC and companion module each store a security key that is generated by the SoC. The key may be a bit string that is generated via a random number generator, thereby obviating the need to utilize hardware secure module (HSM) provisioning and complex encryption hardware. Moreover, the disclosure is directed to supporting additional phases of the manufacturing process, such as debugging and a restoration process that functions to delete or invalidate the keys stored in the SoC and companion module.

公开(公告)号：US11902062B2

公开(公告)日：2024-02-13

申请号：US17754311

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Elan Banin ,  Rotem Banin ,  Ofir Degani ,  Eytan Mann

IPC: H03K9/08 ,  H04L25/49

CPC classification number: H04L25/4902

Abstract: An apparatus for transmitting a bit in addition to a plurality of payload data symbols of a communication protocol is provided. The apparatus comprises an input interface configured to receive information about a bit value of the bit. Further, the apparatus comprises a transmission circuit configured to, if the bit value is a first value, transmit the plurality of payload data symbols at predetermined positions in a data signal as pulses of variable pulse length. The respective pulse length of each of the pulses is selected based on the symbol value of the payload data symbol represented by the respective pulse. If the bit value is a second value, the transmission circuit is configured to transmit a pulse exhibiting a pulse length being longer than a maximum payload data symbol pulse length defined in the communication protocol at the predetermined position of the pulse for the d-th payload data symbol of the plurality of payload data symbols, d=k+i if k+i≤z. d=([k+i] mod z) if k+i>z. k is the symbol value of the i-th payload data symbol of the plurality of payload data symbols, z is the number of possible symbol values of the payload data symbols defined in the communication protocol, and 1≤i≤z.

公开(公告)号：US11387852B2

公开(公告)日：2022-07-12

申请号：US16639780

申请日：2018-09-17

Applicant: Intel Corporation

Inventor： Elan Banin ,  Eytan Mann ,  Rotem Banin ,  Ronen Gernizky ,  Ofir Degani ,  Igal Kushnir ,  Shahar Porat ,  Amir Rubin ,  Vladimir Volokitin ,  Elinor Kashani ,  Dmitry Felsenstein ,  Ayal Eshkoli ,  Tai Davidson ,  Eng Hun Ooi ,  Yossi Tsfati ,  Ran Shimon

IPC: H04B1/04 ,  H04L7/033

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

公开(公告)号：US20220083109A1

公开(公告)日：2022-03-17

申请号：US17384971

申请日：2021-07-26

Applicant: Intel Corporation

Inventor： Raanan Sover ,  Eytan Mann ,  Rafi Ben-Tal ,  Richard S. Perry

IPC: G06F1/18 ,  H05K7/14

Abstract: An electronic device may include a substrate having a substrate body. The electronic device may include a first interconnect region, for example located proximate to a first end of the substrate. The first interconnect region may extend from the substrate body. The first interconnect region may include a first set of interconnects, and the first set of interconnects may be located proximate to the substrate body. The first interconnect region may include a second set of interconnects, and the second set of interconnects may be located remote from the substrate body. The second set of interconnects may be physically separated from the first set of interconnects, for example by an inactive region. The first set of interconnects may be located between the inactive region and the substrate body.

公开(公告)号：US11073873B1

公开(公告)日：2021-07-27

申请号：US16829524

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Raanan Sover ,  Eytan Mann ,  Rafi Ben-Tal ,  Richard S Perry

IPC: G06F1/18 ,  H05K7/14 ,  H01L23/538

Abstract: An electronic device may include a substrate having a substrate body. The electronic device may include a first interconnect region, for example located proximate to a first end of the substrate. The first interconnect region may extend from the substrate body. The first interconnect region may include a first set of interconnects, and the first set of interconnects may be located proximate to the substrate body. The first interconnect region may include a second set of interconnects, and the second set of interconnects may be located remote from the substrate body. The second set of interconnects may be physically separated from the first set of interconnects, for example by an inactive region. The first set of interconnects may be located between the inactive region and the substrate body.

公开(公告)号：US20200212943A1

公开(公告)日：2020-07-02

申请号：US16639780

申请日：2018-09-17

Applicant: Intel Corporation

Inventor： Elan Banin ,  Eytan Mann ,  Rotem Banin ,  Ronen Gernizky ,  Ofir Degani ,  Igal Kushnir ,  Shahar Porat ,  Amir Rubin ,  Vladimir Volokitin ,  Elinor Kashani ,  Dmitry Felsenstein ,  Ayal Eshkoli ,  Tal Davidson ,  Eng Hun Ooi ,  Yossi Tsfati ,  Ran Shimon

IPC: H04B1/04 ,  H04L7/033

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.