公开(公告)号：US11955732B2

公开(公告)日：2024-04-09

申请号：US18089220

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Erkan Alpman ,  Arnaud Lucres Amadjikpe ,  Omer Asaf ,  Kameran Azadet ,  Rotem Banin ,  Miroslav Baryakh ,  Anat Bazov ,  Stefano Brenna ,  Bryan K. Casper ,  Anandaroop Chakrabarti ,  Gregory Chance ,  Debabani Choudhury ,  Emanuel Cohen ,  Claudio Da Silva ,  Sidharth Dalmia ,  Saeid Daneshgar Asl ,  Kaushik Dasgupta ,  Kunal Datta ,  Brandon Davis ,  Ofir Degani ,  Amr M. Fahim ,  Amit Freiman ,  Michael Genossar ,  Eran Gerson ,  Eyal Goldberger ,  Eshel Gordon ,  Meir Gordon ,  Josef Hagn ,  Shinwon Kang ,  Te Yu Kao ,  Noam Kogan ,  Mikko S. Komulainen ,  Igal Yehuda Kushnir ,  Saku Lahti ,  Mikko M. Lampinen ,  Naftali Landsberg ,  Wook Bong Lee ,  Run Levinger ,  Albert Molina ,  Resti Montoya Moreno ,  Tawfiq Musah ,  Nathan G. Narevsky ,  Hosein Nikopour ,  Oner Orhan ,  Georgios Palaskas ,  Stefano Pellerano ,  Ron Pongratz ,  Ashoke Ravi ,  Shmuel Ravid ,  Peter Andrew Sagazio ,  Eren Sasoglu ,  Lior Shakedd ,  Gadi Shor ,  Baljit Singh ,  Menashe Soffer ,  Ra'anan Sover ,  Shilpa Talwar ,  Nebil Tanzi ,  Moshe Teplitsky ,  Chintan S. Thakkar ,  Jayprakash Thakur ,  Avi Tsarfati ,  Yossi Tsfati ,  Marian Verhelst ,  Nir Weisman ,  Shuhei Yamada ,  Ana M. Yepes ,  Duncan Kitchin

IPC: H01Q9/04 ,  H01Q1/24 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q3/24 ,  H01Q5/47 ,  H01Q21/24 ,  H03L7/14 ,  H04B1/3827 ,  H04B7/0456 ,  H04B7/06 ,  H04B15/04

CPC classification number: H01Q9/0414 ,  H01Q1/243 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q3/24 ,  H01Q5/47 ,  H01Q21/24 ,  H03L7/145 ,  H04B1/3827 ,  H04B7/0482 ,  H04B7/0639 ,  H04B15/04

Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

公开(公告)号：US11902062B2

公开(公告)日：2024-02-13

申请号：US17754311

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Elan Banin ,  Rotem Banin ,  Ofir Degani ,  Eytan Mann

IPC: H03K9/08 ,  H04L25/49

CPC classification number: H04L25/4902

Abstract: An apparatus for transmitting a bit in addition to a plurality of payload data symbols of a communication protocol is provided. The apparatus comprises an input interface configured to receive information about a bit value of the bit. Further, the apparatus comprises a transmission circuit configured to, if the bit value is a first value, transmit the plurality of payload data symbols at predetermined positions in a data signal as pulses of variable pulse length. The respective pulse length of each of the pulses is selected based on the symbol value of the payload data symbol represented by the respective pulse. If the bit value is a second value, the transmission circuit is configured to transmit a pulse exhibiting a pulse length being longer than a maximum payload data symbol pulse length defined in the communication protocol at the predetermined position of the pulse for the d-th payload data symbol of the plurality of payload data symbols, d=k+i if k+i≤z. d=([k+i] mod z) if k+i>z. k is the symbol value of the i-th payload data symbol of the plurality of payload data symbols, z is the number of possible symbol values of the payload data symbols defined in the communication protocol, and 1≤i≤z.

公开(公告)号：US20230413195A1

公开(公告)日：2023-12-21

申请号：US17841907

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Evgeny Shumaker ,  Elan Banin ,  Ofir Degani

IPC: H04W56/00

CPC classification number: H04W56/001

Abstract: A radio-head apparatus can comprise memory to store dithering information of the apparatus. The radio-head can further include radio-head circuitry to generate a clock signal according to the dithering information and to provide a wakeup signal, subsequent to commencement of clock signal generation, to instruct a secondary RH to use the clock signal of the RH. The same wakeup signal is also used to synchronize the finite state machines of both RHs that govern and report the dithering information. Synchronization of the FSM allows estimation of information to be used in the secondary RH for compensation of the clock dithering applied in the primary RH. Other systems and apparatuses are described.

公开(公告)号：US20230318643A1

公开(公告)日：2023-10-05

申请号：US17710861

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Elan Banin ,  Assaf Ben-Bassat ,  Ashoke Ravi ,  Rotem Banin ,  Ofir Degani

IPC: H04B1/10 ,  H04B1/00 ,  H04B1/68

CPC classification number: H04B1/10 ,  H04B1/0028 ,  H04B1/005 ,  H04B1/68

Abstract: For example, a transmitter, e.g., for a wireless communication device, may be configured to transmit a wideband Radio Frequency (RF) Transmit (Tx) signal having a wide bandwidth of at least 80 Megahertz (MHz). For example, the transmitter may be configured to generate the wideband RF Tx signal having the wide bandwidth based on a baseband signal. The transmitter may be configured to generate the wideband RF Tx signal including a suppressed third harmonic and a suppressed fifth harmonic.

公开(公告)号：US11387852B2

公开(公告)日：2022-07-12

申请号：US16639780

申请日：2018-09-17

Applicant: Intel Corporation

Inventor： Elan Banin ,  Eytan Mann ,  Rotem Banin ,  Ronen Gernizky ,  Ofir Degani ,  Igal Kushnir ,  Shahar Porat ,  Amir Rubin ,  Vladimir Volokitin ,  Elinor Kashani ,  Dmitry Felsenstein ,  Ayal Eshkoli ,  Tai Davidson ,  Eng Hun Ooi ,  Yossi Tsfati ,  Ran Shimon

IPC: H04B1/04 ,  H04L7/033

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

公开(公告)号：US20200212943A1

公开(公告)日：2020-07-02

申请号：US16639780

申请日：2018-09-17

Applicant: Intel Corporation

Inventor： Elan Banin ,  Eytan Mann ,  Rotem Banin ,  Ronen Gernizky ,  Ofir Degani ,  Igal Kushnir ,  Shahar Porat ,  Amir Rubin ,  Vladimir Volokitin ,  Elinor Kashani ,  Dmitry Felsenstein ,  Ayal Eshkoli ,  Tal Davidson ,  Eng Hun Ooi ,  Yossi Tsfati ,  Ran Shimon

IPC: H04B1/04 ,  H04L7/033

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

公开(公告)号：US09998162B2

公开(公告)日：2018-06-12

申请号：US15282622

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Eshel Gordon ,  Sophia Maerkovich ,  Ofir Degani ,  Hasnain Lakdawala

IPC: H03M1/00 ,  H03M1/66 ,  H04B1/16 ,  H03M1/46 ,  H03M1/10

CPC classification number: H04B1/16 ,  H03M1/04 ,  H03M1/0656 ,  H03M1/0695 ,  H03M1/144 ,  H03M1/145 ,  H03M1/36 ,  H03M1/466

Abstract: Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.

公开(公告)号：US20180097535A1

公开(公告)日：2018-04-05

申请号：US15282622

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Eshel Gordon ,  Sophia Maerkovich ,  Ofir Degani ,  Hasnain Lakdawala

IPC: H04B1/16 ,  H03M1/46 ,  H03M1/10

CPC classification number: H04B1/16 ,  H03M1/04 ,  H03M1/0656 ,  H03M1/0695 ,  H03M1/144 ,  H03M1/145 ,  H03M1/36 ,  H03M1/466

Abstract: Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.

公开(公告)号：US09614574B2

公开(公告)日：2017-04-04

申请号：US14815393

申请日：2015-07-31

Applicant: Intel Corporation

Inventor： Tzvi Maimon ,  Ofir Degani

IPC: H04B1/18 ,  H04B1/48 ,  H04B1/04 ,  H04B1/44 ,  H04W88/06

CPC classification number: H04B1/48 ,  H04B1/0458 ,  H04B1/18 ,  H04B1/44 ,  H04W88/06

Abstract: An apparatus comprises a transmit network to transmit an input from a first amplifier to an antenna, a receive network to provide an input from an antenna to a second amplifier, a first switch to selectively decouple the transmit network from the antenna, and a second switch to selectively decouple the receive network from the antenna. Other embodiments may be described.

公开(公告)号：US20160043471A1

公开(公告)日：2016-02-11

申请号：US14918508

申请日：2015-10-20

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Valluri R. Rao ,  Ofir Degani

IPC: H01Q9/04 ,  H01Q21/00 ,  H01Q1/52

CPC classification number: H01Q9/045 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01P11/00 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q1/526 ,  H01Q21/0006 ,  Y10T29/49018

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming a package structure comprising a discrete antenna disposed on a back side of a device, wherein the discrete antenna comprises an antenna substrate, a through antenna substrate via vertically disposed through the antenna substrate. A through device substrate via that is vertically disposed within the device is coupled with the through antenna substrate via, and a package substrate is coupled with an active side of the device.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法和结构可以包括形成包括设置在设备的背侧的分立天线的封装结构，其中分立天线包括天线基板，通过天线基板垂直设置的通过天线基板。 垂直设置在器件内的穿通器件衬底通孔经由天线衬底与封装衬底耦合，并且封装衬底与器件的有源侧耦合。