公开(公告)号：US20220206864A1

公开(公告)日：2022-06-30

申请号：US17694516

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Sundar NADATHUR ,  Susanne M. BALLE ,  Andrzej KURIATA ,  Duane E. GALBI ,  Nagabhushan CHITLUR ,  Francesc GUIM BERNAT ,  Alexander BACHMUTSKY

IPC: G06F9/50 ,  G06F8/65

Abstract: Examples described herein relate to causing execution of a workload on a device based on characteristics of the device and based on metadata associated with the device identifying execution requirements and software and hardware compatibilities between the device and a platform environment. In some examples, an accelerator device is selected to execute a workload based on characteristics of the accelerator device and based on software and hardware compatibilities between the device and a platform environment of the accelerator device.

公开(公告)号：US20210303477A1

公开(公告)日：2021-09-30

申请号：US17344763

申请日：2021-06-10

Applicant: Intel Corporation

Inventor： Kshitij A. DOSHI ,  Francesc GUIM BERNAT ,  Suraj PRABHAKARAN ,  Tushar Sudhakar GOHAD

IPC: G06F12/1009 ,  G06F12/0813

Abstract: Examples described herein relate to a network interface device. In some examples, the network interface device includes a device interface; input/output circuitry to receive Ethernet compliant packets and output Ethernet compliant packets; circuitry to monitor a particular page for a rate of data copying among nodes within a group of two or more nodes; and circuitry to perform one or more actions based, at least in part, on the rate of data copying among the nodes within the group of two or more nodes to attempt to reduce a number of copy operations of the data among the nodes within the group of two or more nodes, wherein the group of two or more nodes are part of a distributed shared memory (DSM).

公开(公告)号：US20200278804A1

公开(公告)日：2020-09-03

申请号：US16846994

申请日：2020-04-13

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Tushar Sudhakar GOHAD ,  Mark A. SCHMISSEUR ,  Thomas WILLHALM

IPC: G06F3/06 ,  G06N3/063

Abstract: A memory request manager in a memory system registers a tenant for access to a plurality of memory devices, registers one or more service level agreement (SLA) requirements for the tenant for access to the plurality of memory devices, monitors usage of the plurality of memory devices by tenants, receives a memory request from the tenant to access a selected one of the plurality of memory devices, and allows the access when usage of the plurality of memory devices meets the one or more SLA requirements for the tenant.

公开(公告)号：US20200241926A1

公开(公告)日：2020-07-30

申请号：US16726645

申请日：2019-12-24

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT

IPC: G06F9/50

Abstract: Examples described herein relate to validation, security, control, and visibility of the actual hardware and software components allocated in a composite node for a service, tenant, sub-tenant, or customer. Resource certification allows for hardware and software resources to be exposed in an interface to allow obtaining its meta-data and the corresponding certification of its resources. A composite node certification can be exposed so that a tenant, sub-tenant, or customer can access and validate such composite node certification.

公开(公告)号：US20200228630A1

公开(公告)日：2020-07-16

申请号：US16833448

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Dimitrios ZIAKAS ,  Mark A. SCHMISSEUR ,  Ned SMITH

IPC: H04L29/08 ,  H04L12/911 ,  H04L12/66

Abstract: A persistence service for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow an endpoint, such as an IoT device or client device, to specify criteria for achieving persistence for data stored in an edge resource. The persistence interface extends the storage and memory controllers to store data in accordance with the criteria, including determining whether a local or remote edge resource is best able to store data persistently in a manner that satisfies the criteria. The criteria include a persistence service level agreement, including a required time to persistence, cost of persistence and reliability level of persistence. Only edge resources that contain media, including storage subsystems and/or memory, capable of storing data persistently while satisfying the criteria will be permitted to service the request. The persistence service can include a discovery service to efficiently locate objects previously stored using the persistence service.

公开(公告)号：US20200050569A1

公开(公告)日：2020-02-13

申请号：US16473561

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Gaspar MORA PORTA ,  Michael A PARKER ,  Roberto PENARANDA CEBRIAN ,  Albert S. CHENG ,  Francesc GUIM BERNAT

IPC: G06F13/40 ,  H04L12/801 ,  H04L12/937 ,  G06F13/366

Abstract: In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.

公开(公告)号：US20190340089A1

公开(公告)日：2019-11-07

申请号：US16513478

申请日：2019-07-16

Applicant: Intel Corporation

Inventor： Kshitij A. DOSHI ,  Vadim SUKHOMLINOV ,  Francesc GUIM BERNAT

IPC: G06F11/20 ,  G06F1/28 ,  G06F1/30

Abstract: Data is mirrored in persistent memory in nodes in a computer cluster for redundancy. The data can be recovered from the persistent memory in a failed node by another node in the computer cluster through a low power network interface in the failed node.

公开(公告)号：US20190121564A1

公开(公告)日：2019-04-25

申请号：US16221832

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Mustafa HAJEER ,  Thomas Willhalm ,  Amin FIROOZSHAHIAN ,  Chandan EGBERT

IPC: G06F3/06

Abstract: Examples relate to an approximative memory deduplication method, a controller apparatus or controller device for a memory or storage controller, a memory or storage controller, a computer system and to a computer program. The approximative memory deduplication method comprises determining a hash value of a data block. The hash value is based on a user-defined approximative hashing function. The approximative memory deduplication method comprises storing a quantized version of the data block based on the hash value using a memory or storage device of the computer system.

公开(公告)号：US20180278493A1

公开(公告)日：2018-09-27

申请号：US15470664

申请日：2017-03-27

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Thomas WILLHALM ,  Andrew HERDRICH ,  Edwin VERPLANKE

IPC: H04L12/24 ,  H04L12/947 ,  H04L5/00 ,  H04L12/911

CPC classification number: H04L41/5019 ,  H04L5/0055 ,  H04L41/0896 ,  H04L41/5003 ,  H04L47/783 ,  H04L49/25

Abstract: Examples include techniques to meet quality of service (QoS) requirements for a fabric point to point connection. Examples include an application hosted by a compute node coupled with a fabric requesting bandwidth for a point to point connection through the fabric and the request being granted or not granted based at least partially on whether bandwidth is available for allocation to meet one or more QoS requirements.

公开(公告)号：US20240103861A1

公开(公告)日：2024-03-28

申请号：US18533487

申请日：2023-12-08

Applicant: Intel Corporation

Inventor： Akhilesh S. THYAGATURU ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Mohit Kumar GARG

IPC: G06F9/30

CPC classification number: G06F9/3004

Abstract: An apparatus is described. The apparatus includes a memory module. The memory module includes a memory. The memory module includes function execution circuitry. The function execution circuitry is configurable to execute a producer function and a consumer function of a multi-function process. The memory module includes an interface to be coupled to a memory controller.