公开(公告)号：US20200050569A1

公开(公告)日：2020-02-13

申请号：US16473561

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Gaspar MORA PORTA ,  Michael A PARKER ,  Roberto PENARANDA CEBRIAN ,  Albert S. CHENG ,  Francesc GUIM BERNAT

IPC: G06F13/40 ,  H04L12/801 ,  H04L12/937 ,  G06F13/366

Abstract: In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.

公开(公告)号：US20210058334A1

公开(公告)日：2021-02-25

申请号：US16547482

申请日：2019-08-21

Applicant: Intel Corporation

Inventor： John GRETH ,  Arvind SRINIVASAN ,  David ARDITTI ILITZKY ,  Robert SOUTHWORTH ,  Gaspar MORA PORTA ,  Scott DIESING ,  Bongjin JUNG ,  Prasad SHABADI

IPC: H04L12/867 ,  H04L12/911 ,  H04L12/863 ,  H04L12/865

Abstract: Examples described herein provide a packet ingress and egress system with a memory buffer in a network device. The ingress and egress system can generate a time stamp for one or more received packets at an ingress port, allocate a received packet to a queue among multiple queues, and permit egress of a packet from a queue. An ingress port can have one or more queues allocated to store received packets. An egress port can use the one or more queues from which to egress packets. A maximum size of a queue is set as the allocated memory region size divided by the number of ingress ports that use the allocated memory region. An egress arbiter can apply an arbitration scheme to schedule egress of packets in time stamp order.

公开(公告)号：US20210058343A1

公开(公告)日：2021-02-25

申请号：US16546993

申请日：2019-08-21

Applicant: Intel Corporation

Inventor： John GRETH ,  Arvind SRINIVASAN ,  Robert SOUTHWORTH ,  David ARDITTI ILITZKY ,  Bongjin JUNG ,  Gaspar MORA PORTA

IPC: H04L12/935 ,  H04L12/947 ,  H04L12/24 ,  H04L29/06

Abstract: Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.