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公开(公告)号:US20220103484A1
公开(公告)日:2022-03-31
申请号:US17545962
申请日:2021-12-08
Applicant: Intel Corporation
Inventor: Roberto PENARANDA CEBRIAN , Robert SOUTHWORTH , Pedro YEBENES SEGURA , Rong PAN , Allister ALEMANIA , Nayan Amrutlal SUTHAR , Malek MUSLEH
IPC: H04L47/25 , H04L47/27 , H04L47/283
Abstract: Examples described herein relate to a network interface device that is to adjust a transmission rate of packets based on a number of flows contributing to congestion and/or based on whether latency is increasing or decreasing. In some examples, adjusting the transmission rate of packets based on a number of flows contributing to congestion comprises adjust an additive increase (AI) parameter based on the number of flows contributing to congestion. In some examples, latency is based on a measured roundtrip time and a baseline roundtrip time.
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公开(公告)号:US20220210075A1
公开(公告)日:2022-06-30
申请号:US17514615
申请日:2021-10-29
Applicant: Intel Corporation
Inventor: Malek MUSLEH , Gene WU , Anupama KURPAD , Allister ALEMANIA , Roberto PENARANDA CEBRIAN , Robert SOUTHWORTH , Pedro YEBENES SEGURA , Curt E. BRUNS , Sujoy SEN
IPC: H04L12/801 , H04L12/803 , H04L12/835 , H04L12/851
Abstract: Examples described herein relate to a switch, when operational, that is configured to receive in a packet an indicator of number of remaining bytes in a flow and to selectively send a congestion message based on a fullness level of a buffer and indication of remainder of the flow. In some examples, the indicator is received in an Internet Protocol version 4 consistent Options header field or Internet Protocol version 6 consistent Flow label field. In some examples, the congestion message comprises one or more of: an Explicit Congestion Control Notification (ECN), priority-based flow control (PFC), and/or in-band telemetry (INT). In some examples, to selectively send a congestion message to a transmitter based on a fullness level of a buffer that stored the packet and the number of remaining bytes in flow, the switch is to determine whether the buffer is large enough to store the remaining bytes in the flow.
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公开(公告)号:US20220103479A1
公开(公告)日:2022-03-31
申请号:US17545959
申请日:2021-12-08
Applicant: Intel Corporation
Inventor: Pedro YEBENES SEGURA , Roberto PENARANDA CEBRIAN , Rong PAN , Robert SOUTHWORTH , Allister ALEMANIA , Malek MUSLEH
IPC: H04L47/122 , H04L47/11 , H04L47/25 , H04L47/70
Abstract: Examples described herein relate to a sender network interface device transmitting one or more packet probes to a receiver device, when a link is underutilized, to request information concerning link or path utilization. Based on responses to the packet probes, the sender network interface device can determine a packet transmit rate of packets of one or more flows and adjust the packet transmit rate of packets of one or more flows to increase utilization of the link.
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公开(公告)号:US20240267340A1
公开(公告)日:2024-08-08
申请号:US18618254
申请日:2024-03-27
Applicant: Intel Corporation
Inventor: Anil VASUDEVAN , Roberto PENARANDA CEBRIAN , Md Ashiqur RAHMAN , Pedro YEBENES SEGURA , Allister ALEMANIA
IPC: H04L47/70
CPC classification number: H04L47/826
Abstract: Examples described herein relate to a network interface device that includes an interface to a port; and a circuitry. The circuitry can be configured to: receive a first packet that comprises a time stamp associated with a prior or originating transmission of the first packet by a transmitter network interface device; enqueue an entry for the first packet in a queue; and dequeue the entry based at least in part on the time stamp.
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公开(公告)号:US20210359955A1
公开(公告)日:2021-11-18
申请号:US17384627
申请日:2021-07-23
Applicant: Intel Corporation
Inventor: Malek MUSLEH , Tony HURSON , Pedro YEBENES SEGURA , Allister ALEMANIA , Roberto PENARANDA CEBRIAN , Ayan BANERJEE , Robert SOUTHWORTH , Sujoy SEN , Curt E. BRUNS
IPC: H04L12/911 , H04L12/923 , H04L12/927 , G06F15/173
Abstract: Examples described herein relate to a network interface device comprising: a host interface, a direct memory access (DMA) engine, and circuitry to allocate a region in a cache to store a context of a connection. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on connection reliability and wherein connection reliability comprises use of a reliable transport protocol or non-use of a reliable transport protocol. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on expected length of runtime of the connection and the expected length of runtime of the connection is based on a historic average amount of time the context for the connection was stored in the cache. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on content transmitted and the content transmitted comprises congestion messaging payload or acknowledgement. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on application-specified priority level and the application-specified priority level comprises an application-specified traffic class level or class of service level.
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6.
公开(公告)号:US20200050569A1
公开(公告)日:2020-02-13
申请号:US16473561
申请日:2016-12-30
Applicant: Intel Corporation
Inventor: Gaspar MORA PORTA , Michael A PARKER , Roberto PENARANDA CEBRIAN , Albert S. CHENG , Francesc GUIM BERNAT
IPC: G06F13/40 , H04L12/801 , H04L12/937 , G06F13/366
Abstract: In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.
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公开(公告)号:US20240089219A1
公开(公告)日:2024-03-14
申请号:US18388780
申请日:2023-11-10
Applicant: Intel Corporation
Inventor: Md Ashiqur RAHMAN , Roberto PENARANDA CEBRIAN , Anil VASUDEVAN , Allister ALEMANIA , Pedro YEBENES SEGURA
CPC classification number: H04L49/206 , H04L47/621 , H04L49/9063
Abstract: Examples described herein relate to a switch. In some examples, the switch includes circuitry that is configured to: based on receipt of a packet and a level of a first queue, select among a first memory and a second memory device among multiple second memory devices to store the packet, based on selection of the first memory, store the packet in the first memory, and based on selection of the second memory device among multiple second memory devices, store the packet into the selected second memory device. In some examples, the packet is associated with an ingress port and an egress port, and the selected second memory device is associated with a third port that is different than the ingress port or the egress port associated with the packet.
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公开(公告)号:US20230403233A1
公开(公告)日:2023-12-14
申请号:US18239467
申请日:2023-08-29
Applicant: Intel Corporation
Inventor: Md Ashiqur RAHMAN , Rong PAN , Roberto PENARANDA CEBRIAN , Allister ALEMANIA , Pedro YEBENES SEGURA
IPC: H04L47/12 , H04L47/2425 , H04L47/30 , H04L49/9047
CPC classification number: H04L47/12 , H04L47/2425 , H04L47/30 , H04L49/9047
Abstract: Examples described herein relate to a network interface device. In some examples, the network interface device includes a host interface; a direct memory access (DMA) circuitry; a network interface; and circuitry. The circuitry can be configured to: based on received telemetry data from at least one switch: select a next hop network interface device from among multiple network interface devices based on received telemetry data. In some examples, the telemetry data is based on congestion information of a first queue associated with a first traffic class, the telemetry data is based on per-network interface device hop-level congestion states from at least one network interface device, the first queue shares bandwidth of an egress port with a second queue, the first traffic class is associated with packet traffic subject to congestion control based on utilization of the first queue, and the utilization of the first queue is based on a drain rate of the first queue and a transmit rate from the egress port.
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公开(公告)号:US20210092069A1
公开(公告)日:2021-03-25
申请号:US17118409
申请日:2020-12-10
Applicant: Intel Corporation
Inventor: Malek MUSLEH , Anupama KURPAD , Roberto PENARANDA CEBRIAN , Allister ALEMANIA , Pedro YEBENES SEGURA , Curt E. BRUNS , Robert SOUTHWORTH , Sujoy SEN
IPC: H04L12/851 , H04L12/751 , H04L12/853 , H04L12/727 , G06N3/08 , G06N3/04
Abstract: Examples described herein relate to a network interface and at least one processor that is to indicate whether data is associated with a machine learning operation or non-machine learning operation to manage traversal of the data through one or more network elements to a destination network element and cause the network interface to include an indication in a packet of whether the packet includes machine learning data or non-machine learning data. In some examples, the indication in a packet of whether the packet includes machine learning data or non-machine learning data comprises a priority level and wherein one or more higher priority levels identify machine learning data. In some examples, for machine learning data, the priority level is based on whether the data is associated with inference, training, or re-training operations. In some examples, for machine learning data, the priority level is based on whether the data is associated with real-time or time insensitive inference operations.
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