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公开(公告)号:US11132319B2
公开(公告)日:2021-09-28
申请号:US15870679
申请日:2018-01-12
Applicant: Intel Corporation
Inventor: Christopher Wing Hong Ngau , Hooi Kar Loo , Poh Thiam Teoh , Shashitheren Kerisnan , Maxim Dan , Chee Siang Chow
IPC: G06F1/3234 , G06F13/38 , G06F13/40 , H04B10/27 , G06F13/42
Abstract: Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured to receive, at a downstream port of the root port controller, from an upstream switch port, a first power management entry request; reject the first power management entry request; transmit a negative acknowledgement message to the upstream switch port; initiate a timer for at least 20 microseconds; during the 20 microseconds, ignore any power management entry requests received from the upstream switch port; receive, after the expiration of the 20 microseconds, a subsequent power management entry request; accept the subsequent power management entry request; and transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.
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公开(公告)号:US10664433B2
公开(公告)日:2020-05-26
申请号:US15199323
申请日:2016-06-30
Applicant: Intel Corporation
Inventor: Lakshminarayana Pappu , Timothy J. Callahan , Hem Doshi , Hooi Kar Loo , Suketu U. Bhatt
Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers. According to one embodiment there is a functional semiconductor device, having therein a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; virtualized device logic embedded within the serial IO interface; a transaction originator to originate a shuttle transaction and to issue the shuttle transaction onto the device fabric directed toward the serial IO interface; in which the shuttle transaction includes a shuttle header and a shuttle payload having embedded therein one or more passenger transactions for issuance onto the device fabric; in which the virtualized device logic is to receive the shuttle transaction at the serial IO interface via the device fabric; in which the virtualized device logic is to strip the shuttle header from the shuttle transaction to expose the one or more passenger transactions; and in which the virtualized device logic is to issue the one or more passenger transactions onto the device fabric. Other related embodiments are disclosed.
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