公开(公告)号：US09891282B2

公开(公告)日：2018-02-13

申请号：US14998200

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Robert P. Adler ,  Suketu U. Bhatt ,  Robert De Gruijl ,  Kah Meng Yeem

IPC: G01R31/28 ,  G01R31/3177 ,  H03K19/177 ,  H03K19/21

CPC classification number: G01R31/3177 ,  H03K19/17704 ,  H03K19/21

Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.

公开(公告)号：US10657092B2

公开(公告)日：2020-05-19

申请号：US15199302

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Timothy J. Callahan ,  Hem Doshi ,  Hooi Kar Loo ,  Suketu U. Bhatt

IPC: G06F13/42

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing. For instance, in accordance with one embodiment, there is a functional semiconductor device, comprising: a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; virtualized device logic embedded within the serial IO interface; a transaction originator to originate a transaction and issue the transaction onto the device fabric directed toward the serial IO interface; in which the virtualized device logic is to receive the transaction at the serial IO interface via the device fabric; in which the virtualized device logic is to modify the transaction received to form a modified transaction; in which the virtualized device logic is to issue the modified transaction onto the device fabric; and in which the modified transaction is returned to the transaction originator. Other related embodiments are disclosed.

公开(公告)号：US09971644B2

公开(公告)日：2018-05-15

申请号：US14998256

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Suketu U. Bhatt ,  Yuen Tat Lee ,  Lakshminarayana Pappu

IPC: G01R31/28 ,  G06F11/10 ,  G01R31/317

CPC classification number: G06F11/1004 ,  G01R31/31724 ,  G06F11/26

Abstract: One embodiment provides an apparatus. The apparatus includes a functional test controller. The functional test controller includes controller logic to receive communication protocol-specific data comprising a packet header from a tester; a protocol buffer to store the packet header; and a pseudorandom bit sequence (PRBS) generator to generate a PRBS. The controller logic is to combine the packet header and the PRBS into a packet and to provide the packet to an input/output (I/O) controller under test.

公开(公告)号：US10705142B2

公开(公告)日：2020-07-07

申请号：US15394666

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Suketu U. Bhatt ,  Satheesh Chellappan

IPC: G01R31/00 ,  G01R31/317 ,  G06F11/00

Abstract: Techniques and mechanisms for providing on-chip link control functionality to facilitate emulation of a communication. In an embodiment, an integrated circuit (IC) chip includes a physical layer (PHY) which supports communication compatible with a high-speed serial interface standard. A link controller of the IC chip is coupled between the PHY and an interconnect architecture which variously couples a host and other resources of the IC chip to each other. A test controller of the IC chip signals a test mode to implement a loopback path of the link controller in lieu of one or more functional paths for communication with the PHY. In another embodiment, signal output by the loopback path emulate a communication from a resource other than the test controller.

公开(公告)号：US20170184666A1

公开(公告)日：2017-06-29

申请号：US14998200

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Robert P. Adler ,  Suketu U. Bhatt ,  Robert De Gruijl ,  Kah Meng Yeem

IPC: G01R31/3177 ,  H03K19/21 ,  H03K19/177

CPC classification number: G01R31/3177 ,  H03K19/17704 ,  H03K19/21

Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.

公开(公告)号：US10484361B2

公开(公告)日：2019-11-19

申请号：US15199356

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Timothy J. Callahan ,  Baruch Schnarch ,  Hem Doshi ,  Suketu U. Bhatt

IPC: H04L29/06 ,  G06F13/42 ,  G06F11/30 ,  G06F21/85

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS. According to one embodiment there is a functional semiconductor device, having therein a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; a transaction originator to originate a transactions and issue the transactions onto the device fabric directed toward the serial IO interface; in which the virtualized device logic is to receive the transactions at the serial IO interface via the device fabric and return responsive transactions to the device originator based on the transactions received; signature collection logic to collect signal information based on the transactions carried by the device fabric; and a signal accumulator to generate a test signature based on the signal information collected by the signature collection logic. Other related embodiments are disclosed.

公开(公告)号：US20180004685A1

公开(公告)日：2018-01-04

申请号：US15196832

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Suketu U. Bhatt ,  Lakshminarayana Pappu ,  Satheesh Chellappan

IPC: G06F13/10 ,  G06F13/42 ,  G06F13/20 ,  G06F13/40

CPC classification number: G06F13/102 ,  G06F13/20 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2213/0042

Abstract: Described is a host interface, a device interface, a downstream translation circuitry, an upstream translation circuitry, and a host line-state state machine. The host interface may comprise a host line-state output. The device interface may comprise a device line-state output. The downstream translation circuitry may be operable to process a transaction received on the host interface and to generate a transaction for the device interface. The upstream translation circuitry may be operable to process a transaction received on the device interface and to generate a transaction for the host interface. The host line-state state machine may be operable to set the host line-state output to a value that is one of: an SE0-state value, a J-state value, or a K-state value.

公开(公告)号：US20170184667A1

公开(公告)日：2017-06-29

申请号：US14998256

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Suketu U. Bhatt ,  Yuen Tat Lee ,  Lakshminarayana Pappu

IPC: G01R31/3177 ,  G06F11/10

CPC classification number: G06F11/1004 ,  G01R31/31724 ,  G06F11/26

Abstract: One embodiment provides an apparatus. The apparatus includes a functional test controller. The functional test controller includes controller logic to receive communication protocol-specific data comprising a packet header from a tester; a protocol buffer to store the packet header; and a pseudorandom bit sequence (PRBS) generator to generate a PRBS. The controller logic is to combine the packet header and the PRBS into a packet and to provide the packet to an input/output (I/O) controller under test.

公开(公告)号：US10664433B2

公开(公告)日：2020-05-26

申请号：US15199323

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Timothy J. Callahan ,  Hem Doshi ,  Hooi Kar Loo ,  Suketu U. Bhatt

IPC: G06F13/42 ,  H04L29/06 ,  G06F21/82

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers. According to one embodiment there is a functional semiconductor device, having therein a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; virtualized device logic embedded within the serial IO interface; a transaction originator to originate a shuttle transaction and to issue the shuttle transaction onto the device fabric directed toward the serial IO interface; in which the shuttle transaction includes a shuttle header and a shuttle payload having embedded therein one or more passenger transactions for issuance onto the device fabric; in which the virtualized device logic is to receive the shuttle transaction at the serial IO interface via the device fabric; in which the virtualized device logic is to strip the shuttle header from the shuttle transaction to expose the one or more passenger transactions; and in which the virtualized device logic is to issue the one or more passenger transactions onto the device fabric. Other related embodiments are disclosed.

公开(公告)号：US10127162B2

公开(公告)日：2018-11-13

申请号：US15196832

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Suketu U. Bhatt ,  Lakshminarayana Pappu ,  Satheesh Chellappan

IPC: G06F13/10 ,  G06F13/20 ,  G06F13/40 ,  G06F13/42

Abstract: Described is a host interface, a device interface, a downstream translation circuitry, an upstream translation circuitry, and a host line-state state machine. The host interface may comprise a host line-state output. The device interface may comprise a device line-state output. The downstream translation circuitry may be operable to process a transaction received on the host interface and to generate a transaction for the device interface. The upstream translation circuitry may be operable to process a transaction received on the device interface and to generate a transaction for the host interface. The host line-state state machine may be operable to set the host line-state output to a value that is one of: an SE0-state value, a J-state value, or a K-state value.