公开(公告)号：US10884965B2

公开(公告)日：2021-01-05

申请号：US16543934

申请日：2019-08-19

Applicant: INTEL CORPORATION

Inventor： David J. Harriman ,  Maxim Dan

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42

Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.

公开(公告)号：US09396151B2

公开(公告)日：2016-07-19

申请号：US14301100

申请日：2014-06-10

Applicant: INTEL CORPORATION

Inventor： David J. Harriman ,  Maxim Dan

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  G06F13/387 ,  G06F13/4295 ,  G06F2213/0026

Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.

Abstract translation: 描述了跨计算机设备的多协议I / O互连的PCIe隧道的方法，装置和系统的实施例。 跨多协议I / O互连的PCIe隧道的方法可以包括在计算机设备的多协议I / O互连的交换结构的端口之间建立第一通信路径，以响应于外围组件互连express（PCIe ）设备连接到计算机设备，并且在交换结构和PCIe控制器之间建立第二通信路径。 该方法还可以包括通过多协议I / O互连，通过第一和第二通信路径将PCIe设备的PCIe协议分组从PCIe设备路由到PCIe控制器。 可以描述和要求保护其他实施例。

公开(公告)号：US10387348B2

公开(公告)日：2019-08-20

申请号：US15942922

申请日：2018-04-02

Applicant: INTEL CORPORATION

Inventor： David J. Harriman ,  Maxim Dan

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42

Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.

公开(公告)号：US20160140069A1

公开(公告)日：2016-05-19

申请号：US15005279

申请日：2016-01-25

Applicant: INTEL CORPORATION

Inventor： David J. Harriman ,  Maxim Dan

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/387 ,  G06F13/4295 ,  G06F2213/0026

Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.

公开(公告)号：US20210382839A1

公开(公告)日：2021-12-09

申请号：US17412075

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Christopher Wing Hong Ngau ,  Hooi Kar Loo ,  Poh Thiam Teoh ,  Shashitheren Kerisnan ,  Maxim Dan ,  Chee Siang Chow

IPC: G06F13/40 ,  H04B10/27 ,  G06F13/42

Abstract: Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured to receive, at a downstream port of the root port controller, from an upstream switch port, a first power management entry request; reject the first power management entry request; transmit a negative acknowledgement message to the upstream switch port; initiate a timer for at least 20 microseconds; during the 20 microseconds, ignore any power management entry requests received from the upstream switch port; receive, after the expiration of the 20 microseconds, a subsequent power management entry request; accept the subsequent power management entry request; and transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.

公开(公告)号：US11132319B2

公开(公告)日：2021-09-28

申请号：US15870679

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Christopher Wing Hong Ngau ,  Hooi Kar Loo ,  Poh Thiam Teoh ,  Shashitheren Kerisnan ,  Maxim Dan ,  Chee Siang Chow

IPC: G06F1/3234 ,  G06F13/38 ,  G06F13/40 ,  H04B10/27 ,  G06F13/42

Abstract: Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured to receive, at a downstream port of the root port controller, from an upstream switch port, a first power management entry request; reject the first power management entry request; transmit a negative acknowledgement message to the upstream switch port; initiate a timer for at least 20 microseconds; during the 20 microseconds, ignore any power management entry requests received from the upstream switch port; receive, after the expiration of the 20 microseconds, a subsequent power management entry request; accept the subsequent power management entry request; and transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.

公开(公告)号：US09934181B2

公开(公告)日：2018-04-03

申请号：US15005279

申请日：2016-01-25

Applicant: INTEL CORPORATION

Inventor： David J. Harriman ,  Maxim Dan

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4022 ,  G06F13/387 ,  G06F13/4295 ,  G06F2213/0026

Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.

公开(公告)号：US11768791B2

公开(公告)日：2023-09-26

申请号：US17734733

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Reuven Rozic ,  Maxim Dan ,  Prashant Sethi ,  Robert E. Gough ,  Shanthanand Kutuva Rabindranath

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/404 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0024 ,  G06F2213/0026

Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.

公开(公告)号：US20220334994A1

公开(公告)日：2022-10-20

申请号：US17734733

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Reuven Rozic ,  Maxim Dan ,  Prashant Sethi ,  Robert E. Gough ,  Shanthanand Kutuva Rabindranath

IPC: G06F13/40 ,  G06F13/42

Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.

公开(公告)号：US11321264B2

公开(公告)日：2022-05-03

申请号：US17136347

申请日：2020-12-29

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Reuven Rozic ,  Maxim Dan ,  Prashant Sethi ,  Robert E. Gough ,  Shanthanand Kutuva Rabindranath

IPC: G06F13/40 ,  G06F13/42

Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.