公开(公告)号：US20220197519A1

公开(公告)日：2022-06-23

申请号：US17128072

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Chia-Hung Kuo ,  Anoop Mukker ,  Eng Hun Ooi ,  Avishay Snir ,  Shrinivas Venkatraman ,  Kuan Hua Tan ,  Wai Ben Lin

IPC: G06F3/06

Abstract: A multi-level memory architecture scheme to dynamically balance a number of parameters such as power, thermals, cost, latency and performance for memory levels that are progressively further away from the processor in the platform based on how applications are using memory levels that are further away from processor cores. In some examples, the decision making for the state of the far memory (FM) is decentralized. For example, a processor power management unit (p-unit), near memory controller (NMC), and/or far memory host controller (FMHC) makes decisions about the power and/or performance state of the FM at their respective levels. These decisions are coordinated to provide the most optimum power and/or performance state of the FM for a given time. The power and/or performance state of the memories adaptively change to changing workloads and other parameters even when the processor(s) is in a particular power state.

公开(公告)号：US11080223B2

公开(公告)日：2021-08-03

申请号：US16513941

申请日：2019-07-17

Applicant: Intel Corporation

Inventor： Kuan Hua Tan ,  Eng Hun Ooi ,  Ang Li

IPC: G06F13/42 ,  G06F9/445

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

公开(公告)号：US11038749B2

公开(公告)日：2021-06-15

申请号：US16231807

申请日：2018-12-24

Applicant: INTEL CORPORATION

Inventor： Ang Li ,  Eng Hun Ooi ,  Kuan Hua Tan

IPC: G06F15/177 ,  H04L12/24 ,  G06F12/02 ,  G06F9/30 ,  G06F9/50 ,  H04L29/06

Abstract: A handshake communication mechanism between a host and an end-point device permits multiple Base Address Registers (BAR registers) to be configured to size or resize the mapped address spaces associated with each BAR register. In one embodiment, the handshake communication mechanism includes a single address space reconfiguration request which may be transmitted in a single transaction layer packet, to request the configuration of multiple BAR registers of an end-point device. Other features and advantages may be realized, depending upon the particular application.

公开(公告)号：US10977197B2

公开(公告)日：2021-04-13

申请号：US16367846

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Kuan Hua Tan ,  Ang Li ,  Eng Hun Ooi

IPC: G06F1/26 ,  G06F1/32 ,  G06F13/16 ,  G06F1/3234 ,  G06F9/30 ,  G06F9/50 ,  G06F1/3206

Abstract: Systems and devices can include a power management controller to determine a low power mode exit timing from a plurality of low power mode exit timing options, and cause the setting of a low power mode control register based on the determined low power mode exit timing. A message generator can generate a power mode request message. The power mode request message indicating the determined low power mode exiting timing. The power mode request message can be transmitted to a host across a multilane link.

公开(公告)号：US20200278733A1

公开(公告)日：2020-09-03

申请号：US16875898

申请日：2020-05-15

Applicant: Intel Corporation

Inventor： Ang Li ,  David J. Harriman ,  Kuan Hua Tan

IPC: G06F1/28 ,  G06F1/04 ,  G06F13/42

Abstract: An interface of a device is used to couple to another device and includes a set of data pins to support high speed data communication on an interconnect link between the devices based on an interconnect protocol. The interface further includes at least one auxiliary pin to support a particular signal defined by the interconnect protocol. The device is further configurated to generate hint data for use by the other device and send the hint data as a sideband signal to the other device over the auxiliary pin, where the sideband signal is distinct from signals defined for the auxiliary pin by the interconnect protocol.