公开(公告)号：US11080194B2

公开(公告)日：2021-08-03

申请号：US16234135

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Sreenivas Subramoney ,  Stanislav Shwartsman ,  Anant Nori ,  Shankar Balachandran ,  Elad Shtiegmann ,  Vineeth Mekkat ,  Manjunath Shevgoor ,  Sourabh Alurkar

IPC: G06F12/0862

Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.

公开(公告)号：US10860319B2

公开(公告)日：2020-12-08

申请号：US15941976

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Mark Dechene ,  Manjunath Shevgoor ,  Faruk Guvenilir ,  Zhongying Zhang ,  Jonathan Perry

IPC: G06F9/30 ,  G06F9/32 ,  G06F12/1027 ,  G06F9/38

Abstract: An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the execution circuitry including an address generation unit (AGU) to generate an effective address to be used for the load operation; and early page prediction (EPP) circuitry to use one or more attributes associated with the load instruction to predict a physical page address for the load instruction simultaneously with the AGU generating the effective address and/or prior to generation of the effective address.

公开(公告)号：US10678692B2

公开(公告)日：2020-06-09

申请号：US15709285

申请日：2017-09-19

Applicant: INTEL CORPORATION

Inventor： Seth H. Pugsley ,  Manjunath Shevgoor ,  Christopher B. Wilkerson

IPC: G06F12/0862 ,  G06F9/30 ,  G06F12/0811 ,  G06F12/0806 ,  G06F12/0897

Abstract: In one embodiment, a processor comprises a first prefetcher to generate prefetch requests to prefetch data into a mid-level cache; a second prefetcher to generate prefetch requests to prefetch data into the mid-level cache; and a prefetcher selector to select a prefetcher configuration for the first prefetcher and the second prefetcher based on at least one memory access metric, wherein the prefetcher configuration is to specify whether the first prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of a particular page and whether the second prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of the particular page.

公开(公告)号：US10437590B2

公开(公告)日：2019-10-08

申请号：US15719290

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Sofia Pediaditaki ,  Ethan Schuchman ,  Rangeen Basu Roy Chowdhury ,  Manjunath Shevgoor

IPC: G06F12/00 ,  G06F9/30 ,  G06F12/0846 ,  G06F12/128 ,  G06F9/52 ,  G06F12/0811

Abstract: Embodiments of apparatuses, methods, and systems for inter-cluster communication of live-in register values are described. In an embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which to store a value to be produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters. The cache memory is separate from a system memory hierarchy and a register set of the processor.