公开(公告)号：US11553346B2

公开(公告)日：2023-01-10

申请号：US16729250

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Liuyang Lily Yang ,  Manoj R. Sastry ,  Xiruo Liu ,  Moreno Ambrosin

IPC: H04W12/12 ,  H04W12/122 ,  H04W4/40 ,  H04W8/00 ,  G08G1/16 ,  G05D1/00 ,  H04W48/02

Abstract: A first roadway system receives a communication from a second roadway system over a wireless channel, where the communication includes a description of a physical object within a driving environment. Characteristics of the physical object are determined based on sensors of the first roadway system. The communication is determined to contain an anomaly based on a comparison of the description of the physical object with the characteristics determined based on the sensors of the first roadway system. Misbehavior data is generated to describe the anomaly. A remedial action is initiated based on the anomaly.

公开(公告)号：US10826710B2

公开(公告)日：2020-11-03

申请号：US16682635

申请日：2019-11-13

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj R. Sastry

IPC: H04L29/06 ,  H04L9/32 ,  G09C1/00 ,  H04L9/30

Abstract: Technologies for elliptic curve cryptography (ECC) include a computing device having an ECC engine that reads one or more parameters from a data port. The ECC engine performs operations using the parameters, such as an Elliptic Curve Digital Signature Algorithm (ECDSA). The ECDSA may be performed in a protected mode, in which the ECC engine will ignore inputs. The ECC engine may perform the ECDSA in a fixed amount of time in order to protect against timing side-channel attacks. The ECC engine may perform the ECDSA by consuming a uniform amount of power in order to protect against power side-channel attacks. The ECC engine may perform the ECDSA by emitting a uniform amount of electromagnetic radiation in order to protect against EM side-channel attacks. The ECC engine may perform the ECDSA verify with 384-bit output in order to protect against fault injection attacks.

公开(公告)号：US10715335B2

公开(公告)日：2020-07-14

申请号：US16026657

申请日：2018-07-03

Applicant: Intel Corporation

Inventor： Steffen Schulz ,  Rafael Misoczki ,  Manoj R. Sastry ,  Jesse Walker

IPC: H04L29/06 ,  H04L9/32 ,  H04L29/08 ,  H04L9/08 ,  G06F8/65 ,  H04L9/14 ,  H04L9/30

Abstract: In a method for validating software updates, a data processing system contains a current version of a software component. The data processing system saves at least first and second current advance keys (AKs). After saving the current AKs, the data processing system receives an update package for a new version of the software component. The data processing system extracts a digital signature and two or more new AKs from the update package. The data processing system uses at least one current AK to determine whether the digital signature is valid. In response to a determination that the digital signature is valid, the data processing system uses a software image from the update package to update the software component, and the data processing system saves the new AKs, for subsequent utilization as the current AKs.

公开(公告)号：US10404468B2

公开(公告)日：2019-09-03

申请号：US15351606

申请日：2016-11-15

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj R. Sastry ,  Jesse Walker ,  Li Zhao ,  Rafael Misoczki

IPC: G06F11/30 ,  G06F12/14 ,  H04L9/32 ,  H04L9/06

Abstract: Technologies for counter with CBC-MAC (CCM) mode encryption include a computing device that performs a CBC-MAC authentication operation on a message with an encryption key, using a 64-bit block cipher to generate a message authentication code. The computing device generates a first 64-bit authentication block including an 8-bit flag field and a length field of between 11 and 32 bits. The flag field indicates the length of the length field. Performing the CBC-MAC authentication operation includes formatting the message into one or more 64-bit authentication blocks. The computing device performs a counter mode encryption operation on the message with the encryption key using the 64-bit block cipher to generate a cipher text. Performing the counter mode encryption includes generating multiple 64-bit keystream blocks. The computing device generates an authentication tag based on the message authentication code and a first keystream block of keystream blocks. Other embodiments are described and claimed.

公开(公告)号：US20190052654A1

公开(公告)日：2019-02-14

申请号：US16026413

申请日：2018-07-03

Applicant: Intel Corporation

Inventor： Marcio Juliato ,  Shabbir Ahmed ,  Santosh Ghosh ,  Manoj R. Sastry

IPC: H04L29/06 ,  G06F21/64 ,  H04L29/08 ,  H04L12/40

Abstract: A data processing system that provides for active prevention of masquerading attacks comprises a microcontroller, a transceiver, and an active attack prevention module (AAPM) in communication with the microcontroller and the transceiver. The microcontroller enables the data processing system to operate as a node in a vehicle control system (VCS). The transceiver enables the node to communicate with a local area network (LAN) of the VCS. The AAPM enables the node to monitor the LAN for messages. In response to detecting a message on the LAN, the AAPM automatically determines whether the message falsely identifies the node as a source, based on a value in an identifier field in the message. In response to determining that the message falsely identifies the node as the source, the AAPM automatically takes at least one remedial action to neutralize the message. Other embodiments are described and claimed.

公开(公告)号：US20180091309A1

公开(公告)日：2018-03-29

申请号：US15277462

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Steffen Schulz ,  Manoj R. Sastry ,  Santosh Ghosh ,  Li Zhao

IPC: H04L9/32

CPC classification number: H04L9/3247 ,  H04L9/3242 ,  H04L9/3252 ,  H04L2209/30 ,  H04L2209/38

Abstract: One embodiment provides a signer device. The signer device includes hash signature control logic and signer signature logic. The hash signature control logic is to retrieve a first nonce, to concatenate the first nonce and a message to be transmitted and to determine whether a first message representative satisfies a target threshold. The signer signature logic is to generate a first transmitted signature based, at least in part, on the first message representative, if the first message representative satisfies the target threshold. The hash signature control logic is to retrieve a second nonce, concatenate the second nonce and the message to be transmitted and to determine whether a second message representative satisfies the target threshold, if the first message representative does not satisfy the target threshold.

公开(公告)号：US20170372088A1

公开(公告)日：2017-12-28

申请号：US15190396

申请日：2016-06-23

Applicant: INTEL CORPORATION

Inventor： Li Zhao ,  Manoj R. Sastry ,  Arnab Raha

IPC: G06F21/62

Abstract: Lightweight trusted execution technologies for internet-of-things devices are described. In response to a memory request at a page unit from an application executing in a current domain, the page unit is to map a current virtual address (VA) to a current physical address (PA). The policy enforcement logic (PEL) reads, from a secure domain cache (SDC), a domain value (DID) and a VA value that correspond to the current PA. The PEL grants access when the current domain and the DID correspond to the unprotected region or the current domain and the DID correspond to the secure domain region, the current domain is equal to the DID, and the current VA is equal to the VA value. The PEL grants data access and denies code access when the current domain corresponds to the secure domain region and the DID corresponds to the unprotected region.

公开(公告)号：US20170187530A1

公开(公告)日：2017-06-29

申请号：US14757658

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj R. Sastry

IPC: H04L9/30 ,  H04L9/14

CPC classification number: H04L9/3066 ,  G06F7/725 ,  G09C1/00 ,  H04L9/14 ,  H04L2209/12 ,  H04L2209/24

Abstract: Embodiments of a system for, and method for using, an elliptic curve cryptography integrated circuit are generally described herein. An elliptic curve cryptography (ECC) operation request may be received. One of a plurality of circuit portions may be instructed to perform the ECC operation. The plurality of circuit portions that may be used include a finite field arithmetic circuit portion, an EC point addition and doubler circuit portion, a finite field exponentiation circuit portion, and a point multiplier circuit portion. The result of the ECC operation may then be output.

公开(公告)号：US12148061B2

公开(公告)日：2024-11-19

申请号：US17133076

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Vuk Lesi ,  Qian Wang ,  Christopher Gutierrez ,  Marcio Rogerio Juliato ,  Shabbir Ahmed ,  Manoj R. Sastry

IPC: G06Q50/47

Abstract: Systems and techniques for malicious request detection in automated resource dispatch are described herein. A request for a resource may be received from a user device. A location may be obtained for delivery of the resource. Sensor data may be retrieved for the location. The sensor data and user profile data may be evaluated to determine if the request is malicious. A disincentivizing message may be generated based on the determination that the request is malicious. In response to receipt of a response to the disincentivizing message, a resource may be dispatched to the location.

公开(公告)号：US20230376637A1

公开(公告)日：2023-11-23

申请号：US18363176

申请日：2023-08-01

Applicant: Intel Corporation

Inventor： Manoj R. Sastry ,  Alpa Narendra Trivedi ,  Men Long

IPC: G06F21/72 ,  G09C1/00 ,  G06F21/85 ,  H04L9/06 ,  H04L9/08

CPC classification number: G06F21/72 ,  G09C1/00 ,  G06F21/85 ,  H04L9/0643 ,  H04L9/0897 ,  H04L2209/76 ,  G06F2213/0038 ,  G06F2207/7219 ,  G06F2211/008

Abstract: Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.