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公开(公告)号:US20190155540A1
公开(公告)日:2019-05-23
申请号:US16161818
申请日:2018-10-16
Applicant: Intel Corporation
Inventor: Ahmad Yasin , Stanislav Bratanov
Abstract: Systems and method are disclosed for monitoring processor performance. Embodiments described relate to differentiating function performance by input parameters. In one embodiment, a method includes configuring a counter contained in a processor to count occurrences of an event in the processor and to overflow upon the count of occurrences reaching a specified value, configuring a precise event based sampling (PEBS) handler circuit to generate and store a PEBS record into a PEBS memory buffer after at least one overflow, the PEBS record containing at least one stack entry read from a stack after the at least one overflow, enabling the PEBS handler circuit to generate and store the PEBS record after the at least one overflow, generating and storing the PEBS record into the PEBS memory buffer after the at least one overflow; and storing contents of the PEBS memory buffer to a PEBS trace file in a memory.
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公开(公告)号:US09965375B2
公开(公告)日:2018-05-08
申请号:US15194881
申请日:2016-06-28
Applicant: INTEL CORPORATION
Inventor: Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
CPC classification number: G06F11/3636 , G06F9/45558 , G06F2009/45591 , H04L41/0613 , H04L43/04
Abstract: A core includes a memory buffer and executes an instruction within a virtual machine. A processor tracer captures trace data and formats the trace data as trace data packets. An event-based sampler generates field data for a sampling record in response to occurrence of an event of a certain type as a result of execution of the instruction. The processor tracer, upon receipt of the field data: formats the field data into elements of the sampling record as a group of record packets; inserts the group of record packets between the trace data packets as a combined packet stream; and stores the combined packet stream in the memory buffer as a series of output pages. The core, when in guest profiling mode, executes a virtual machine monitor to map output pages of the memory buffer to host physical pages of main memory using multilevel page tables.
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公开(公告)号:US20180088861A1
公开(公告)日:2018-03-29
申请号:US15277855
申请日:2016-09-27
Applicant: Intel Corporation
Inventor: Ahmad Yasin , Stanislav Bratanov
IPC: G06F3/06 , G06F12/0875 , G06F9/38 , G06F11/30
CPC classification number: G06F3/0656 , G06F3/061 , G06F3/0683 , G06F9/30 , G06F9/3802 , G06F11/3024 , G06F11/3466 , G06F12/0875
Abstract: Systems and method are disclosed for monitoring processor performance. Embodiments described relate to differentiating function performance by input parameters. In one embodiment, a method includes configuring a counter contained in a processor to count occurrences of an event in the processor and to overflow upon the count of occurrences reaching a specified value, configuring a precise event based sampling (PEBS) handler circuit to generate and store a PEBS record into a PEBS memory buffer after at least one overflow, the PEBS record containing at least one stack entry read from a stack after the at least one overflow, enabling the PEBS handler circuit to generate and store the PEBS record after the at least one overflow, generating and storing the PEBS record into the PEBS memory buffer after the at least one overflow; and storing contents of the PEBS memory buffer to a PEBS trace file in a memory.
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