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    VIRTUALIZING PRECISE EVENT BASED SAMPLING
    1.
    发明申请
    VIRTUALIZING PRECISE EVENT BASED SAMPLING 审中-公开

    公开(公告)号：US20200242003A1

    公开(公告)日：2020-07-30

    申请号：US16699871

    申请日：2019-12-02

    Applicant: Intel Corporation

    Inventor： Matthew C. Merten ,  Beeman C. Strong ,  Michael W. Chynoweth ,  Grant G. Zhou ,  Andreas Kleen ,  Kimberly C. Weier ,  Angela D. Schmid ,  Stanislav Bratanov ,  Seth Abraham ,  Jason W. Brandt ,  Ahmad Yasin

    IPC: G06F11/36 ,  G06F9/455

    Abstract: A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.

    Instruction and logic for interrupt and exception handling
    2.
    发明授权
    Instruction and logic for interrupt and exception handling 有权

    公开(公告)号：US10445204B2

    公开(公告)日：2019-10-15

    申请号：US14865715

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Richard B. O'Connor ,  Beeman C. Strong ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar

    IPC: G06F9/38 ,  G06F11/30

    Abstract: A processor includes a processor trace logical unit to produce branch execution records from execution of instructions. The processor further includes logic to determine that a condition has occurred on the processor during execution of the instructions. The condition is to include an asynchronous event or a return from a software handler for an asynchronous event. The processor further includes logic to determine whether event tracing is enabled for the processor. The processor also includes logic to generate a control flow event (CFE) packet. The CFE packet is to indicate a type of the condition. The processor further includes logic to generate an indicator of an instruction address that generated the condition.

    Heterogeneous CPUID spoofing for remote processors
    3.
    发明授权
    Heterogeneous CPUID spoofing for remote processors 有权

    公开(公告)号：US11055094B2

    公开(公告)日：2021-07-06

    申请号：US16453531

    申请日：2019-06-26

    Applicant: Intel Corporation

    Inventor： Toby Opferman ,  Russell C. Arnold ,  Vedvyas Shanbhogue ,  Michael W. Chynoweth

    IPC: G06F9/30

    Abstract: Disclosed embodiments relate to improved heterogeneous CPUID spoofing for remote processors. In one example, a system includes multiple processors, including a first processor including configuration circuitry to enable remote processor identification (ID) spoofing; fetch circuitry to fetch an instruction; decode circuitry to decode the instruction having fields to specify an opcode and a context, the opcode indicating execution circuitry is to: when remote processor ID spoofing is enabled, access a processor ID spoofing data structure storing processor ID information for each of the plurality of processors, and report processor ID information for a processor identified by the context; and, when remote processor ID spoofing is not enabled, report processor ID information for the first processor; and execution circuitry to execute the instruction as per the opcode.

    Monitoring performance of a processing device to manage non-precise events
    7.
    发明授权
    Monitoring performance of a processing device to manage non-precise events 有权

    公开(公告)号：US09766999B2

    公开(公告)日：2017-09-19

    申请号：US14292140

    申请日：2014-05-30

    Applicant: Intel Corporation

    Inventor： Jonathan D. Combs ,  Michael W. Chynoweth ,  Jason W. Brandt ,  Corey D. Gough

    IPC: G06F11/00 ,  G06F11/34

    CPC classification number: G06F11/348 ,  G06F11/3466 ,  G06F2201/86 ,  G06F2201/88

    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processing device to manage non-precise events. A processing device includes a performance counter to increment upon occurrence of a non-precise event in the processing device. The processing device also includes a precise event based sampling (PEBS) enable control communicably coupled to the performance counter. The processing device also includes a PEBS handler to generate and store a PEBS record including an architectural metadata defining a state of the processing device at a time of generation of the PEBS record. The processing device further includes a non-precise event based sampling (NPEBS) module communicably coupled to the PEBS control and the PEBS handler. The NPEBS module causes the PEBS handler to generate the PEBS record for the non-precise event upon overflow of the performance counter.

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