-
1.
公开(公告)号:US10261792B2
公开(公告)日:2019-04-16
申请号:US15408632
申请日:2017-01-18
Applicant: Intel Corporation
Inventor: Michael W. Chynoweth , Peggy J. Irelan , Matthew C. Merten , Seung-Woo Kim , Laura A. Knauth , Stanislav Bratanov
IPC: G06F9/30 , G06F11/34 , G06F12/0875
Abstract: In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.
-
公开(公告)号:US11055203B2
公开(公告)日:2021-07-06
申请号:US16699871
申请日:2019-12-02
Applicant: Intel Corporation
Inventor: Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
Abstract: A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.
-
3.
公开(公告)号:US20170132004A1
公开(公告)日:2017-05-11
申请号:US15408632
申请日:2017-01-18
Applicant: Intel Corporation
Inventor: Michael W. Chynoweth , Peggy J. Irelan , Matthew C. Merten , Seung-Woo Kim , Laura A. Knauth , Stanislav Bratanov
IPC: G06F9/30 , G06F12/0875
CPC classification number: G06F9/30058 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/3016 , G06F11/3409 , G06F11/3476 , G06F11/348 , G06F12/0875
Abstract: In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.
-
公开(公告)号:US20180253370A1
公开(公告)日:2018-09-06
申请号:US15972390
申请日:2018-05-07
Applicant: INTEL CORPORATION
Inventor: Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
CPC classification number: G06F11/3636 , G06F9/45558 , G06F2009/45591 , H04L41/0613 , H04L43/04
Abstract: A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.
-
公开(公告)号:US20170371769A1
公开(公告)日:2017-12-28
申请号:US15194881
申请日:2016-06-28
Applicant: INTEL CORPORATION
Inventor: Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
CPC classification number: G06F11/3636 , G06F9/45558 , G06F2009/45591 , H04L41/0613 , H04L43/04
Abstract: A core includes a memory buffer and executes an instruction within a virtual machine. A processor tracer captures trace data and formats the trace data as trace data packets. An event-based sampler generates field data for a sampling record in response to occurrence of an event of a certain type as a result of execution of the instruction. The processor tracer, upon receipt of the field data: formats the field data into elements of the sampling record as a group of record packets; inserts the group of record packets between the trace data packets as a combined packet stream; and stores the combined packet stream in the memory buffer as a series of output pages. The core, when in guest profiling mode, executes a virtual machine monitor to map output pages of the memory buffer to host physical pages of main memory using multilevel page tables.
-
公开(公告)号:US11954465B2
公开(公告)日:2024-04-09
申请号:US17643856
申请日:2021-12-13
Applicant: Intel Corporation
Inventor: Alexei Katranov , Stanislav Bratanov
CPC classification number: G06F8/41 , G06F8/53 , G06F9/30094 , G06F9/30032
Abstract: An apparatus comprising at least one interface configured to read one or more high-level code instructions; and at least one processor configured to read the one or more high-level code instructions using the interface, determine atomic operations in the high-level code instructions, and translate the one or more high-level code instructions into assembly code instructions, wherein atomic operations are indicated in the assembly code instructions based on the atomic operations in the high-level code instruction.
-
公开(公告)号:US10969995B2
公开(公告)日:2021-04-06
申请号:US16161818
申请日:2018-10-16
Applicant: Intel Corporation
Inventor: Ahmad Yasin , Stanislav Bratanov
Abstract: Systems and method are disclosed for monitoring processor performance. Embodiments described relate to differentiating function performance by input parameters. In one embodiment, a method includes configuring a counter contained in a processor to count occurrences of an event in the processor and to overflow upon the count of occurrences reaching a specified value, configuring a precise event based sampling (PEBS) handler circuit to generate and store a PEBS record into a PEBS memory buffer after at least one overflow, the PEBS record containing at least one stack entry read from a stack after the at least one overflow, enabling the PEBS handler circuit to generate and store the PEBS record after the at least one overflow, generating and storing the PEBS record into the PEBS memory buffer after the at least one overflow; and storing contents of the PEBS memory buffer to a PEBS trace file in a memory.
-
公开(公告)号:US20200242003A1
公开(公告)日:2020-07-30
申请号:US16699871
申请日:2019-12-02
Applicant: Intel Corporation
Inventor: Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
Abstract: A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.
-
公开(公告)号:US10140056B2
公开(公告)日:2018-11-27
申请号:US15277855
申请日:2016-09-27
Applicant: Intel Corporation
Inventor: Ahmad Yasin , Stanislav Bratanov
IPC: G06F3/06 , G06F12/0875 , G06F9/38 , G06F11/30 , G06F11/34
Abstract: Systems and method are disclosed for monitoring processor performance. Embodiments described relate to differentiating function performance by input parameters. In one embodiment, a method includes configuring a counter contained in a processor to count occurrences of an event in the processor and to overflow upon the count of occurrences reaching a specified value, configuring a precise event based sampling (PEBS) handler circuit to generate and store a PEBS record into a PEBS memory buffer after at least one overflow, the PEBS record containing at least one stack entry read from a stack after the at least one overflow, enabling the PEBS handler circuit to generate and store the PEBS record after the at least one overflow, generating and storing the PEBS record into the PEBS memory buffer after the at least one overflow; and storing contents of the PEBS memory buffer to a PEBS trace file in a memory.
-
公开(公告)号:US20230315470A1
公开(公告)日:2023-10-05
申请号:US17708933
申请日:2022-03-30
Applicant: Intel Corporation
Inventor: Matthew Merten , Beeman Strong , Moshe Cohen , Ahmad Yasin , Andreas Kleen , Stanislav Bratanov , Karthik Gopalakrishnan , Angela Schmid , Grant Zhou
CPC classification number: G06F9/3814 , G06F9/30101 , G06F9/321 , G06F11/3409
Abstract: Techniques and mechanisms for configuring processor event-based sampling (PEBS) with a set of control registers. In an embodiment, a first control register of a processor is programmed to store a physical address of a location in a buffer which receives PEBS records. The first control register is further programmed or otherwise configured to store an indication of a size of the buffer. A second control register of the processor stores a physical address of a location in the buffer were a next PEBS record is to be stored. In another embodiment, the processor further comprises multiple control registers which variously configure PEBS generation on a per-counter basis.
-
-
-
-
-
-
-
-
-