公开(公告)号：US10277707B2

公开(公告)日：2019-04-30

申请号：US14778026

申请日：2014-06-26

Applicant: Intel Corporation ,  Xiangbin Wu ,  Shunyu Zhu ,  Yingzhe Shen ,  Tin-Fook Ngai

Inventor： Xiangbin Wu ,  Shunyu Zhu ,  Yingzhe Shen ,  Tin-Fook Ngai

IPC: G06F15/167 ,  H04L29/08 ,  G06F17/30 ,  H04L29/06

Abstract: Apparatuses, methods and storage medium associated with a memcached system are disclosed herewith. In embodiments, a client device of the memcached system may include memory and one or more processors coupled with the memory. Further, the client device may include memcached logic configured to receive a request to Get or Set a value corresponding to a key in the memcached system, determine, in response to the receive, whether the key results in a hit in a local cache maintained in memory by the memcached logic, and service the Get or Set request based at least in part on whether a result of the determine indicates the key results in a hit in the local cache. In embodiments, a server of the memcached system may include complement memcached logic to server a Get, Set or an Update request. Other embodiments may be described and/or claimed.

公开(公告)号：US20160285997A1

公开(公告)日：2016-09-29

申请号：US14778026

申请日：2014-06-26

Applicant: Xiangbin Wu ,  Shunyu Zhu ,  Yingzhe Shen ,  Tin-Fook Ngai ,  Intel Corporation

Inventor： Xiangbin Wu ,  Shunyu Zhu ,  Yingzhe Shen ,  Tin-Fook Ngai

IPC: H04L29/08 ,  H04L29/06 ,  G06F17/30

CPC classification number: H04L67/2852 ,  G06F17/30902 ,  H04L67/10 ,  H04L67/42

Abstract: Apparatuses, methods and storage medium associated with a memcached system are disclosed herewith. In embodiments, a client device of the memcached system may include memory and one or more processors coupled with the memory. Further, the client device may include memcached logic configured to receive a request to Get or Set a value corresponding to a key in the memcached system, determine, in response to the receive, whether the key results in a hit in a local cache maintained in memory by the memcached logic, and service the Get or Set request based at least in part on whether a result of the determine indicates the key results in a hit in the local cache. In embodiments, a server of the memcached system may include complement memcached logic to server a Get, Set or an Update request. Other embodiments may be described and/or claimed.

Abstract translation: 本文公开了与memcached系统相关联的装置，方法和存储介质。 在实施例中，memcached系统的客户端设备可以包括存储器和与存储器耦合的一个或多个处理器。 此外，客户端设备可以包括被配置为接收获取或设置与memcached系统中的密钥对应的值的请求的memcached逻辑，响应于接收确定密钥是否导致本地高速缓存中的命中被保持在 存储器通过memcached逻辑，并且至少部分地基于确定的结果是否指示在本地高速缓存中的命中的关键结果来服务Get或Set请求。 在实施例中，memcached系统的服务器可以包括用于服务Get，Set或Update请求的补码memcached逻辑。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20140237303A1

公开(公告)日：2014-08-21

申请号：US13997664

申请日：2011-12-23

Applicant: INTEL CORPORATION

Inventor： Jayashankar Bharadwaj ,  Victor W. Lee ,  Kim Daehyun ,  Nalini Vasudevan ,  Tin-Fook Ngai ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043

Abstract: An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.

Abstract translation: 描述了用于检测和响应处理器中的故障状况的装置和方法。 例如，一种方法的一个实施例包括：从第一向量寄存器连续读取每个有源元件，每个有源元件指定用于集合或加载操作的地址; 检测与一个或多个所述有源元件相关联的一个或多个故障状况; 对于在除了所述第一有源元件之外的元件的检测到的故障状况之前连续读取的每个有源元件，将从与所述有源元件相关联的地址加载的数据存储在第一输出向量寄存器中; 并且对于与检测到的故障状况相关联的每个有源元件并且跟随检测到的故障状况，设置输出屏蔽寄存器中的位以指示检测到的故障状况。