公开(公告)号：US20210311891A1

公开(公告)日：2021-10-07

申请号：US17354302

申请日：2021-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christoph Raisch ,  Marco Kraemer ,  Frank Siegfried Lehnert ,  Matthias Klein ,  Jonathan D. Bradbury ,  Christian Jacobi ,  Peter Dana Driever ,  Brenton Belmar

IPC: G06F13/16 ,  G06F9/30

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

公开(公告)号：US20210232502A1

公开(公告)日：2021-07-29

申请号：US17226592

申请日：2021-04-09

Applicant: International Business Machines Corporation

Inventor： Christian Zoellin ,  Christian Jacobi ,  Chung-Lung K. Shum ,  Martin Recktenwald ,  Anthony Saporito ,  Aaron Tsai

IPC: G06F12/0817 ,  G06F12/0831

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

公开(公告)号：US11068303B2

公开(公告)日：2021-07-20

申请号：US16278936

申请日：2019-02-19

Applicant: International Business Machines Corporation

Inventor： Avery Francois ,  Gregory William Alexander ,  Christian Jacobi

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/38 ,  G06F9/22

Abstract: A computer-implemented method is provided and includes allocating, by a processor, an instruction to a first thread, decoding, by the processor, the instruction, determining, by the processor, a type of the instruction based on information obtained by decoding the instruction, and based on determining that the instruction is a disruptive complex instruction, changing a mode of allocating hardware resources to an instruction-based allocation mode. In the instruction-based allocation mode, the processor adjusts allocation of the hardware resources among a first thread and a second thread based on types of instructions allocated to the first and second threads.

公开(公告)号：US11010276B2

公开(公告)日：2021-05-18

申请号：US16591256

申请日：2019-10-02

Applicant: International Business Machines Corporation

Inventor： Giles R. Frazier ,  Michael K. Gschwind ,  Christian Jacobi ,  Chung-Lung K. Shum

IPC: G06F11/36 ,  G06F11/07 ,  G06F8/41 ,  G06F9/445

Abstract: A method, computer program product, and system performing a method that include a processor defining a code fingerprint by obtaining parameters describing at least one of an event type or an event. The code fingerprint includes a first sequence. The processor loads the code fingerprint into a register accessible to the processor. Concurrent with executing a program, the processor obtains the code fingerprint from the register and identifies the code fingerprint in the program by comparing a second sequence in the program to the first sequence. Based on identifying the code fingerprint in the program, the processor alerts a runtime environment where the program is executing.

公开(公告)号：US11010066B2

公开(公告)日：2021-05-18

申请号：US16457398

申请日：2019-06-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dan F. Greiner ,  Christian Jacobi ,  Marcel Mitran ,  Volodymyr Paprotski ,  Anthony Saporito ,  Timothy J. Slegel

IPC: G06F3/06 ,  G06F9/46 ,  G06F12/02 ,  G06F12/14

Abstract: A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.

公开(公告)号：US11003452B2

公开(公告)日：2021-05-11

申请号：US16444694

申请日：2019-06-18

Applicant: International Business Machines Corporation

Inventor： Michael K. Gschwind ,  Christian Jacobi ,  Anthony Saporito ,  Chung-Lung K. Shum

IPC: G06F9/38 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862

Abstract: A method, system, and computer program product are provided for prioritizing prefetch instructions. The method includes a processor issuing a prefetch instruction and fetching elements from a cache that can include a memory or a higher level cache. The processor stores the elements in temporary storage and monitors for accesses by an instruction. The processor stores a record representing the prefetch instruction. The processor updates the record with an indicator and issues a new prefetch instruction by comparing the new prefetch instruction to the record, based on the new prefetch instruction matching the prefetch instruction, assigning the indicator to the new prefetch instruction as a priority value, based on the new prefetch instruction not matching the prefetch instruction, assigning a default value to the new prefetch instruction as the priority value, and determining whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction.

公开(公告)号：US20210109758A1

公开(公告)日：2021-04-15

申请号：US17128501

申请日：2020-12-21

Applicant: International Business Machines Corporation

Inventor： Avery Francois ,  Christian Jacobi ,  Gregory William Alexander

IPC: G06F9/38

Abstract: A computer data processing system includes an instruction pipeline having a front end and a back end, a decoding and dispatch unit to dispatch a current instruction; and a pipeline by-pass unit to invoke an out-of-order pipeline by-pass operation. The pipeline by-pass unit by-passes a section of the instruction pipeline such that the current instruction architecturally completes before initiating instruction execution. The computer data processing system further includes a post-completion execution unit that executes the current instruction after the current instruction architecturally completes.

公开(公告)号：US10949212B2

公开(公告)日：2021-03-16

申请号：US16933037

申请日：2020-07-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. Giamei ,  Martin Recktenwald ,  Donald W. Schmidt ,  Timothy Siegel ,  Aditya N. Puranik ,  Mark S. Farrell ,  Christian Jacobi ,  Jonathan D. Bradbury ,  Christian Zoellin

IPC: G06F9/22 ,  G06F9/38 ,  G06F9/30

Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

公开(公告)号：US10824426B2

公开(公告)日：2020-11-03

申请号：US16382740

申请日：2019-04-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jane H. Bartik ,  Christian Jacobi ,  David Lee ,  Jang-Soo Lee ,  Anthony Saporito ,  Christian Zoellin

IPC: G06F9/30 ,  G06F11/36 ,  G06F9/38

Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.

公开(公告)号：US20200264920A1

公开(公告)日：2020-08-20

申请号：US16278936

申请日：2019-02-19

Applicant: International Business Machines Corporation

Inventor： Avery Francois ,  Gregory William Alexander ,  Christian Jacobi

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/22 ,  G06F9/38

Abstract: A computer-implemented method is provided and includes allocating, by a processor, an instruction to a first thread, decoding, by the processor, the instruction, determining, by the processor, a type of the instruction based on information obtained by decoding the instruction, and based on determining that the instruction is a disruptive complex instruction, changing a mode of allocating hardware resources to an instruction-based allocation mode. In the instruction-based allocation mode, the processor adjusts allocation of the hardware resources among a first thread and a second thread based on types of instructions allocated to the first and second threads.