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    Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors
    11.
    发明授权
    Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors 有权
    改善场效应晶体管负偏压温度不稳定性（NBTI）寿命的技术

    公开(公告)号：US07629653B1

    公开(公告)日：2009-12-08

    申请号：US11827765

    申请日：2007-07-13

    申请人： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

    发明人： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823857 ,  H01L21/823842

    摘要： In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

    摘要翻译： 在一个实施例中，集成电路包括具有包括P +掺杂栅极多晶硅层和氮化栅极氧化物（NGOX）层的栅极堆叠的PMOS晶体管。 NGOX层可以在硅衬底之上。 集成电路还包括形成在晶体管上的互连线。 互连线包括吸氢材料，并且可以包括单一材料或材料堆。 互连线有利地吸收否则将被捕获在NGOX层/硅衬底界面中的氢（例如，H 2或H 2 O），从而改善晶体管的负偏压温度不稳定性（NBTI）寿命。

    SONOS type stacks for nonvolatile change trap memory devices and methods to form the same
    12.
    发明授权
    SONOS type stacks for nonvolatile change trap memory devices and methods to form the same 有权
    用于非易失性变换陷阱存储器件的SONOS型堆栈及其形成方法

    公开(公告)号：US08163660B2

    公开(公告)日：2012-04-24

    申请号：US12413389

    申请日：2009-03-27

    申请人： Helmut Puchner ,  Igor Polishchuk ,  Sagy Levy

    发明人： Helmut Puchner ,  Igor Polishchuk ,  Sagy Levy

    IPC分类号： H01L21/31

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

    摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.

    摘要翻译： 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括在基板的表面上形成第一氧化物层。 第一氧化物层暴露于具有第一偏压的第一去耦等离子体氮化工艺。 随后，在第一氧化物层上形成电荷俘获层。 电荷捕获层暴露于氧化过程，然后暴露于具有第二不同偏压的第二去耦等离子体氮化工艺。

    SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Methods to Form the Same
    15.
    发明申请
    SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Methods to Form the Same 有权
    SONOS类型堆叠用于非易失性更换存储器件及其形成方法

    公开(公告)号：US20100041222A1

    公开(公告)日：2010-02-18

    申请号：US12413389

    申请日：2009-03-27

    申请人： Helmut Puchner ,  Igor Polishchuk ,  Sagy Levy

    发明人： Helmut Puchner ,  Igor Polishchuk ,  Sagy Levy

    IPC分类号： H01L21/8246

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

    摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.

    摘要翻译： 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括在基板的表面上形成第一氧化物层。 第一氧化物层暴露于具有第一偏压的第一去耦等离子体氮化工艺。 随后，在第一氧化物层上形成电荷俘获层。 电荷捕获层暴露于氧化过程，然后暴露于具有第二不同偏压的第二去耦等离子体氮化工艺。

    Stress liner for integrated circuits
    16.
    发明授权
    Stress liner for integrated circuits 有权
    集成电路应力衬垫

    公开(公告)号：US07384833B2

    公开(公告)日：2008-06-10

    申请号：US11350160

    申请日：2006-02-07

    申请人： Igor Polishchuk ,  Krishnaswamy Ramkumar ,  Sagy Charel Levy

    发明人： Igor Polishchuk ,  Krishnaswamy Ramkumar ,  Sagy Charel Levy

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

    摘要： In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.

    摘要翻译： 在一个实施例中，通过电介质层形成自对准接触（SAC）沟槽结构以暴露MOS晶体管的有源区。 SAC沟槽结构不仅暴露用于电连接的有源区，而且还去除了有源区上的应力衬垫的部分。 这使得应力衬垫主要在MOS晶体管的侧壁和顶部上方。 在有源区上去除应力衬垫的部分基本上消除了由衬底上的应力衬垫施加的应变的横向分量，从而允许改进的驱动电流而不会使互补MOS晶体管基本上降级。

    Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors
    17.
    发明授权
    Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors 有权
    改善场效应晶体管负偏压温度不稳定性（NBTI）寿命的技术

    公开(公告)号：US07256087B1

    公开(公告)日：2007-08-14

    申请号：US11018422

    申请日：2004-12-21

    申请人： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

    发明人： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823842

    摘要： In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

    摘要翻译： 在一个实施例中，集成电路包括具有包括P +掺杂栅极多晶硅层和氮化栅极氧化物（NGOX）层的栅极堆叠的PMOS晶体管。 NGOX层可以在硅衬底之上。 集成电路还包括形成在晶体管上的互连线。 互连线包括吸氢材料，并且可以包括单一材料或材料堆。 互连线有利地吸收否则将被捕获在NGOX层/硅衬底界面中的氢（例如，H 2 H 2或H 2 O 2），从而提高负偏压温度 晶体管的不稳定性（NBTI）寿命。

    Active Stylus with Capacitive Buttons and Sliders
    18.
    发明申请
    Active Stylus with Capacitive Buttons and Sliders 有权
    活动触笔与电容按钮和滑块

    公开(公告)号：US20130106796A1

    公开(公告)日：2013-05-02

    申请号：US13335522

    申请日：2011-12-22

    申请人： Esat Yilmaz ,  Vemund Kval Bakken ,  Igor Polishchuk ,  Kishore Sundara-Rajan

    发明人： Esat Yilmaz ,  Vemund Kval Bakken ,  Igor Polishchuk ,  Kishore Sundara-Rajan

    IPC分类号： G06F3/033

    CPC分类号： G06F3/0383 ,  G06F3/03545

    摘要： In one embodiment, a device includes a form factor of a stylus. The form factor includes a surface area. The device also includes one or more substrates disposed along one or more portions of the surface area; and one or more touch sensors disposed on one or more of the substrates. At least one of the touch sensors includes a distinct touch-sensitive area that includes a touch-sensitive button, a touch-sensitive wheel, or a touch-sensitive slider. The device also includes a computer-readable non-transitory storage medium coupled to one or more of the touch sensors and embodying logic configured to associate the distinct touch-sensitive area with a pre-determined function of the device.

    摘要翻译： 在一个实施例中，设备包括触控笔的外形尺寸。 外形尺寸包括表面积。 该装置还包括沿表面区域的一个或多个部分设置的一个或多个基板; 以及设置在一个或多个基板上的一个或多个触摸传感器。 触摸传感器中的至少一个包括具有触敏按钮，触敏轮或触敏滑块的不同的触敏区域。 该设备还包括耦合到一个或多个触摸传感器的计算机可读的非暂时性存储介质，并且被配置为将不同的触敏区域与设备的预定功能相关联的体现逻辑。

    Active stylus with capacitive buttons and sliders
    20.
    发明授权
    Active stylus with capacitive buttons and sliders 有权
    具有电容按钮和滑块的活动触控笔

    公开(公告)号：US09354728B2

    公开(公告)日：2016-05-31

    申请号：US13335522

    申请日：2011-12-22

    申请人： Esat Yilmaz ,  Vemund Kval Bakken ,  Igor Polishchuk ,  Kishore Sundara-Rajan

    发明人： Esat Yilmaz ,  Vemund Kval Bakken ,  Igor Polishchuk ,  Kishore Sundara-Rajan

    IPC分类号： G06F3/038 ,  G06F3/0354

    CPC分类号： G06F3/0383 ,  G06F3/03545

    摘要： In one embodiment, a device includes a form factor of a stylus. The form factor includes a surface area. The device also includes one or more substrates disposed along one or more portions of the surface area; and one or more touch sensors disposed on one or more of the substrates. At least one of the touch sensors includes a distinct touch-sensitive area that includes a touch-sensitive button, a touch-sensitive wheel, or a touch-sensitive slider. The device also includes a computer-readable non-transitory storage medium coupled to one or more of the touch sensors and embodying logic configured to associate the distinct touch-sensitive area with a pre-determined function of the device.

    摘要翻译： 在一个实施例中，设备包括触控笔的外形尺寸。 外形尺寸包括表面积。 该装置还包括沿表面区域的一个或多个部分设置的一个或多个基板; 以及设置在一个或多个基板上的一个或多个触摸传感器。 触摸传感器中的至少一个包括具有触敏按钮，触敏轮或触敏滑块的不同的触敏区域。 该设备还包括耦合到一个或多个触摸传感器的计算机可读的非暂时性存储介质，并且被配置为将不同的触敏区域与设备的预定功能相关联的体现逻辑。