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    SONOS type stacks for nonvolatile change trap memory devices and methods to form the same
    1.
    发明授权
    SONOS type stacks for nonvolatile change trap memory devices and methods to form the same 有权
    用于非易失性变换陷阱存储器件的SONOS型堆栈及其形成方法

    公开(公告)号：US08163660B2

    公开(公告)日：2012-04-24

    申请号：US12413389

    申请日：2009-03-27

    申请人： Helmut Puchner ,  Igor Polishchuk ,  Sagy Levy

    发明人： Helmut Puchner ,  Igor Polishchuk ,  Sagy Levy

    IPC分类号： H01L21/31

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

    摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.

    摘要翻译： 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括在基板的表面上形成第一氧化物层。 第一氧化物层暴露于具有第一偏压的第一去耦等离子体氮化工艺。 随后，在第一氧化物层上形成电荷俘获层。 电荷捕获层暴露于氧化过程，然后暴露于具有第二不同偏压的第二去耦等离子体氮化工艺。

    SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Methods to Form the Same
    2.
    发明申请
    SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Methods to Form the Same 有权
    SONOS类型堆叠用于非易失性更换存储器件及其形成方法

    公开(公告)号：US20100041222A1

    公开(公告)日：2010-02-18

    申请号：US12413389

    申请日：2009-03-27

    申请人： Helmut Puchner ,  Igor Polishchuk ,  Sagy Levy

    发明人： Helmut Puchner ,  Igor Polishchuk ,  Sagy Levy

    IPC分类号： H01L21/8246

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

    摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.

    摘要翻译： 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括在基板的表面上形成第一氧化物层。 第一氧化物层暴露于具有第一偏压的第一去耦等离子体氮化工艺。 随后，在第一氧化物层上形成电荷俘获层。 电荷捕获层暴露于氧化过程，然后暴露于具有第二不同偏压的第二去耦等离子体氮化工艺。

    Nonvolatile charge trap memory device having a high dielectric constant blocking region
    3.
    发明授权
    Nonvolatile charge trap memory device having a high dielectric constant blocking region 有权
    具有高介电常数阻挡区域的非易失性电荷陷阱存储器件

    公开(公告)号：US09431549B2

    公开(公告)日：2016-08-30

    申请号：US13436875

    申请日：2012-03-31

    申请人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

    发明人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

    IPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L27/115

    CPC分类号： H01L29/7923 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11578 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66833 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/792 ,  H01L29/7926

    摘要： An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.

    摘要翻译： 描述了非易失性电荷陷阱存储器件的实施例。 在一个实施例中，该装置包括一个通道，该沟道包括覆盖在电连接存储器件的第一扩散区和第二扩散区的衬底上的表面的硅以及与沟道的至少一部分相交并且覆盖的栅极堆，栅极 包括邻接通道的隧道氧化物的堆叠，邻接隧道氧化物的分裂电荷捕获区域和与分离的电荷捕获区域邻接的多层阻挡电介质。 分离电荷捕获区域包括第一电荷捕获层，其包含更接近隧道氧化物的氮化物，以及包含覆盖在第一电荷俘获层上的氮化物的第二电荷俘获层。 多层阻挡电介质至少包括高K电介质层。

    Memory transistor with multiple charge storing layers and a high work function gate electrode
    4.
    发明授权
    Memory transistor with multiple charge storing layers and a high work function gate electrode 有权
    具有多个电荷存储层和高功函数栅电极的存储晶体管

    公开(公告)号：US08859374B1

    公开(公告)日：2014-10-14

    申请号：US13288919

    申请日：2011-11-03

    申请人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

    发明人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

    IPC分类号： H01L21/336

    CPC分类号： H01L29/513 ,  G11C16/0466 ,  G11C16/349 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/28035 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

    摘要： Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method comprises: (i) forming an oxide-nitride-oxide (ONO) dielectric stack on a surface of a semiconductor substrate in at least a first region in which a non-volatile memory transistor is to be formed, the ONO dielectric stack including a multi-layer charge storage layer; (ii) forming an oxide layer on the surface of the substrate in a second region in which a metal oxide semiconductor (MOS) logic transistor is to be formed; and (iii) forming a high work function gate electrode on a surface of the ONO dielectric stack. Other embodiments are also disclosed.

    摘要翻译： 提供包括非易失性存储晶体管的半导体器件及其制造方法以改善其性能。 在一个实施例中，该方法包括：（i）在其中将形成非易失性存储晶体管的至少第一区域中，在半导体衬底的表面上形成氧化物 - 氧化物 - 氧化物（ONO）电介质叠层， ONO电介质堆叠包括多层电荷存储层; （ii）在要形成金属氧化物半导体（MOS）逻辑晶体管的第二区域中在所述衬底的表面上形成氧化物层; 和（iii）在ONO电介质叠层的表面上形成高功函数栅电极。 还公开了其他实施例。

    NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A HIGH DIELECTRIC CONSTANT BLOCKING REGION
    8.
    发明申请
    NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A HIGH DIELECTRIC CONSTANT BLOCKING REGION 有权
    具有高介电常数阻塞区域的非挥发性电荷捕获存储器件

    公开(公告)号：US20130175604A1

    公开(公告)日：2013-07-11

    申请号：US13436875

    申请日：2012-03-31

    申请人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

    发明人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7923 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11578 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66833 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/792 ,  H01L29/7926

    摘要： An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.

    摘要翻译： 描述了非易失性电荷陷阱存储器件的实施例。 在一个实施例中，该装置包括一个通道，该沟道包括覆盖在电连接存储器件的第一扩散区和第二扩散区的衬底上的表面的硅以及与沟道的至少一部分相交并且覆盖的栅极堆，栅极 包括邻接通道的隧道氧化物的堆叠，邻接隧道氧化物的分裂电荷捕获区域和与分离的电荷捕获区域邻接的多层阻挡电介质。 分离电荷捕获区域包括第一电荷捕获层，其包含更接近隧道氧化物的氮化物，以及包含覆盖在第一电荷俘获层上的氮化物的第二电荷俘获层。 多层阻挡电介质至少包括高K电介质层。