公开(公告)号：US20200327270A1

公开(公告)日：2020-10-15

申请号：US16848934

申请日：2020-04-15

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott ,  Robert McKemey ,  Max Freiburghaus

IPC: G06F30/3323

Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

公开(公告)号：US20240176939A1

公开(公告)日：2024-05-30

申请号：US18375466

申请日：2023-09-30

Applicant: Imagination Technologies Limited

Inventor： Faizan Nazar ,  Robert McKemey

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: A hardware design for a component that implements a permutation respecting function is verified to be permutation respecting for a plurality of input vector permutations over all valid input vectors. For each input vector permutation in the plurality of input vector permutations, it is verified that the hardware design is permutation respecting for the input vector permutation by verifying that (i) an output of an instantiation of the hardware design in response to any input vector in a set of input vectors and (ii) an output of an instantiation of the hardware design in response to the input vector permutation of that input vector, are permutation related. The set of input vectors is selected based on an assumption that the hardware design is permutation respecting for at least one other input vector permutation of the plurality of input vector permutations.

公开(公告)号：US20230085107A1

公开(公告)日：2023-03-16

申请号：US17990518

申请日：2022-11-18

Applicant: Imagination Technologies Limited

Inventor： Robert McKemey

IPC: G06F30/323 ,  G06F30/398 ,  G06F30/337

Abstract: Methods and systems for verifying a hardware design for a multi-stage component configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled is stall independent. For each stage from the second stage to the last stage: a relevant portion of the output data of an instantiation of the hardware design is verified as the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs. The relevant portion of the output data of the hardware design is verified as the same if the instantiation is in the same state (i) when that stage is enabled in a cycle and any subsequent stages are enabled in subsequent cycles by a second minimal sequence of inputs and (ii) when that stage is stalled, then that stage is enabled in the next cycle and the subsequent stages are enabled in subsequent cycles by the second minimal sequence of inputs.

公开(公告)号：US20220391205A1

公开(公告)日：2022-12-08

申请号：US17881386

申请日：2022-08-04

Applicant: Imagination Technologies Limited

Inventor： Thomas Rose ,  Max Freiburghaus ,  Robert McKemey

IPC: G06F9/30 ,  G06F7/48 ,  G06F7/50 ,  G06F7/57 ,  G06F7/552

Abstract: A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by 1 / d i . The hardware logic comprises a plurality of multipliers and adders arranged to implement a mth-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.

公开(公告)号：US11106847B2

公开(公告)日：2021-08-31

申请号：US16848934

申请日：2020-04-15

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott ,  Robert McKemey ,  Max Freiburghaus

IPC: G06F30/3323 ,  G06F119/16

Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.