公开(公告)号：US12061233B2

公开(公告)日：2024-08-13

申请号：US18193509

申请日：2023-03-30

Applicant: Imagination Technologies Limited

Inventor： Faizan Nazar ,  Kenneth Rovers

IPC: G01R31/317

CPC classification number: G01R31/31727

Abstract: An error detection circuit and method for performing cyclic redundancy check on a clock gated register signal is disclosed. The error detection circuit comprise a first register, a second register, a third register and an error detection module. The first register is a clock gated register and is configured to be updated with a data signal (x) in response to a clock enabling signal. The second register is configured to be updated with a check bit (c) based on the data signal (x). The check bit is calculated by a check bit calculation unit. The third register is configured to be updated with a current value (b) of the clock enabling signal. The error detection module is configured for calculating an indication bit (I) based on at least the output of the first register, the output of the second register and the output of the third register.

公开(公告)号：US20230409287A1

公开(公告)日：2023-12-21

申请号：US18129019

申请日：2023-03-30

Applicant: Imagination Technologies Limited

Inventor： Kenneth Rovers ,  Faizan Nazar

IPC: G06F7/50 ,  G06F7/523 ,  G06F5/01

CPC classification number: G06F7/50 ,  G06F7/523 ,  G06F5/01

Abstract: Accumulator hardware logic includes first and second addition logic units and a store. The first addition logic unit comprises a first input, a second input and an output, each of the first and second inputs arranged to receive an input value in each clock cycle. The second addition logic unit comprises a first input that is connected directly to the output of the first addition logic unit. It also comprises a second input and an output. The store is arranged to store a result output by the second addition logic unit. The accumulator hardware logic further comprises shifting hardware and/or negation hardware positioned in a feedback path between the store and the second input of the second addition logic unit. The shifting hardware is configured to perform a shift by a fixed number of bit positions in a fixed direction.

公开(公告)号：US20240176939A1

公开(公告)日：2024-05-30

申请号：US18375466

申请日：2023-09-30

Applicant: Imagination Technologies Limited

Inventor： Faizan Nazar ,  Robert McKemey

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: A hardware design for a component that implements a permutation respecting function is verified to be permutation respecting for a plurality of input vector permutations over all valid input vectors. For each input vector permutation in the plurality of input vector permutations, it is verified that the hardware design is permutation respecting for the input vector permutation by verifying that (i) an output of an instantiation of the hardware design in response to any input vector in a set of input vectors and (ii) an output of an instantiation of the hardware design in response to the input vector permutation of that input vector, are permutation related. The set of input vectors is selected based on an assumption that the hardware design is permutation respecting for at least one other input vector permutation of the plurality of input vector permutations.

公开(公告)号：US20210294949A1

公开(公告)日：2021-09-23

申请号：US17207030

申请日：2021-03-19

Applicant: Imagination Technologies Limited

Inventor： Simon Gaulter ,  Thomas Ferrere ,  Faizan Nazar ,  Sam Elliott

IPC: G06F30/33

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

公开(公告)号：US12229002B2

公开(公告)日：2025-02-18

申请号：US18193446

申请日：2023-03-30

Applicant: Imagination Technologies Limited

Inventor： Faizan Nazar ,  Kenneth Rovers

IPC: G06F11/10 ,  G01R31/317

Abstract: An error detection circuit and a method for performing a cyclic redundancy check on a clock gated register signal are disclosed. The error detection circuit comprising a first register, a check bit processing logic and an error detection module. The first register is a clock gated register configured to be updated with a data signal (x) in response to a clock enabling signal. The check bit processing logic configured to, in response to a control signal, update a second register with a check bit, wherein the control signal (b) is the same as the clock enabling signal. The error detection module configured for calculating an indication bit based on at least the output of the first register and the output of the second register.

公开(公告)号：US20240037303A1

公开(公告)日：2024-02-01

申请号：US18377746

申请日：2023-10-06

Applicant: Imagination Technologies Limited

Inventor： Simon Gaulter ,  Thomas Ferrere ,  Faizan Nazar ,  Sam Elliott

IPC: G06F30/33

CPC classification number: G06F30/33

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

公开(公告)号：US20230384375A1

公开(公告)日：2023-11-30

申请号：US18193509

申请日：2023-03-30

Applicant: Imagination Technologies Limited

Inventor： Faizan Nazar ,  Kenneth Rovers

IPC: G01R31/317

CPC classification number: G01R31/31727

Abstract: An error detection circuit and method for performing cyclic redundancy check on a clock gated register signal is disclosed. The error detection circuit comprise a first register, a second register, a third register and an error detection module. The first register is a clock gated register and is configured to be updated with a data signal (x) in response to a clock enabling signal. The second register is configured to be updated with a check bit (c) based on the data signal (x). The check bit is calculated by a check bit calculation unit. The third register is configured to be updated with a current value (b) of the clock enabling signal. The error detection module is configured for calculating an indication bit (I) based on at least the output of the first register, the output of the second register and the output of the third register.

公开(公告)号：US20230384374A1

公开(公告)日：2023-11-30

申请号：US18193446

申请日：2023-03-30

Applicant: Imagination Technologies Limited

Inventor： Faizan Nazar ,  Kenneth Rovers

IPC: G01R31/317

CPC classification number: G01R31/31727

Abstract: An error detection circuit and a method for performing a cyclic redundancy check on a clock gated register signal are disclosed. The error detection circuit comprising a first register, a check bit processing logic and an error detection module. The first register is a clock gated register configured to be updated with a data signal (x) in response to a clock enabling signal. The check bit processing logic configured to, in response to a control signal, update a second register with a check bit, wherein the control signal (b) is the same as the clock enabling signal. The error detection module configured for calculating an indication bit based on at least the output of the first register and the output of the second register.

公开(公告)号：US11783105B2

公开(公告)日：2023-10-10

申请号：US17207030

申请日：2021-03-19

Applicant: Imagination Technologies Limited

Inventor： Simon Gaulter ,  Thomas Ferrere ,  Faizan Nazar ,  Sam Elliott

IPC: G06F30/30 ,  G06F30/33

CPC classification number: G06F30/33

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.